sparc.h (REG_ALLOC_ORDER, [...]): Tweak, and add more detailed comments.

2002-05-03  David S. Miller  <davem@redhat.com>

	* config/sparc/sparc.h (REG_ALLOC_ORDER, REG_LEAF_ALLOC_ORDER):
	Tweak, and add more detailed comments.

From-SVN: r53144

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e3a50302d35d22e4f8f789c5794eb36f06d9d6f1..7d887654802e91cae5629b4970397a05fb8642c2 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2002-05-03  David S. Miller  <davem@redhat.com>
+
+       * config/sparc/sparc.h (REG_ALLOC_ORDER, REG_LEAF_ALLOC_ORDER):
+       Tweak, and add more detailed comments.
+
 2002-05-03  Zack Weinberg  <zack@codesourcery.com>
 
        * Re-apply patch accidentally reverted with

diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index f582b6a45ed3870205f788377c9fdf2223ee9e79..f807be89e54ce4b2691400d4a826508c612e95f0 100644 (file)
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -1273,16 +1273,31 @@ extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
 
 /* This is the order in which to allocate registers normally.  
    
-   We put %f0/%f1 last among the float registers, so as to make it more
+   We put %f0-%f7 last among the float registers, so as to make it more
    likely that a pseudo-register which dies in the float return register
-   will get allocated to the float return register, thus saving a move
-   instruction at the end of the function.  */
+   area will get allocated to the float return register, thus saving a move
+   instruction at the end of the function.
+
+   Similarly for integer return value registers.
+
+   We know in this case that we will not end up with a leaf function.
+
+   The register allocater is given the global and out registers first
+   because these registers are call clobbered and thus less useful to
+   global register allocation.
+
+   Next we list the local and in registers.  They are not call clobbered
+   and thus very useful for global register allocation.  We list the input
+   registers before the locals so that it is more likely the incoming
+   arguments received in those registers can just stay there and not be
+   reloaded.  */
 
 #define REG_ALLOC_ORDER \
-{ 8, 9, 10, 11, 12, 13, 2, 3,          \
-  15, 16, 17, 18, 19, 20, 21, 22,      \
-  23, 24, 25, 26, 27, 28, 29, 31,      \
-  34, 35, 36, 37, 38, 39,              /* %f2-%f7 */   \
+{ 1, 2, 3, 4, 5, 6, 7,                 /* %g1-%g7 */   \
+  13, 12, 11, 10, 9, 8,                /* %o5-%o0 */   \
+  15,                                  /* %o7 */       \
+  16, 17, 18, 19, 20, 21, 22, 23,      /* %l0-%l7 */   \
+  29, 28, 27, 26, 25, 24, 31,          /* %i5-%i0,%i7 */\
   40, 41, 42, 43, 44, 45, 46, 47,      /* %f8-%f15 */  \
   48, 49, 50, 51, 52, 53, 54, 55,      /* %f16-%f23 */ \
   56, 57, 58, 59, 60, 61, 62, 63,      /* %f24-%f31 */ \
@@ -1290,30 +1305,48 @@ extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
   72, 73, 74, 75, 76, 77, 78, 79,      /* %f40-%f47 */ \
   80, 81, 82, 83, 84, 85, 86, 87,      /* %f48-%f55 */ \
   88, 89, 90, 91, 92, 93, 94, 95,      /* %f56-%f63 */ \
-  32, 33,                              /* %f0,%f1 */   \
-  96, 97, 98, 99, 100,                 /* %fcc0-3, %icc */ \
-  1, 4, 5, 6, 7, 0, 14, 30, 101}
+  39, 38, 37, 36, 35, 34, 33, 32,      /* %f7-%f0 */   \
+  96, 97, 98, 99,                      /* %fcc0-3 */   \
+  100, 0, 14, 30, 101}                 /* %icc, %g0, %o6, %i6, %sfp */
 
 /* This is the order in which to allocate registers for
-   leaf functions.  If all registers can fit in the "gi" registers,
-   then we have the possibility of having a leaf function.  */
+   leaf functions.  If all registers can fit in the global and
+   output registers, then we have the possibility of having a leaf
+   function.
+
+   The macro actually mentioned the input registers first,
+   because they get renumbered into the output registers once
+   we know really do have a leaf function.
+
+   To be more precise, this register allocation order is used
+   when %o7 is found to not be clobbered right before register
+   allocation.  Normally, the reason %o7 would be clobbered is
+   due to a call which could not be transformed into a sibling
+   call.
+
+   As a consequence, it is possible to use the leaf register
+   allocation order and not end up with a leaf function.  We will
+   not get suboptimal register allocation in that case because by
+   definition of being potentially leaf, there were no function
+   calls.  Therefore, allocation order within the local register
+   window is not critical like it is when we do have function calls.  */
 
 #define REG_LEAF_ALLOC_ORDER \
-{ 2, 3, 24, 25, 26, 27, 28, 29,                \
-  4, 5, 6, 7, 1,                       \
-  15, 8, 9, 10, 11, 12, 13,            \
-  16, 17, 18, 19, 20, 21, 22, 23,      \
-  34, 35, 36, 37, 38, 39,              \
-  40, 41, 42, 43, 44, 45, 46, 47,      \
-  48, 49, 50, 51, 52, 53, 54, 55,      \
-  56, 57, 58, 59, 60, 61, 62, 63,      \
-  64, 65, 66, 67, 68, 69, 70, 71,      \
-  72, 73, 74, 75, 76, 77, 78, 79,      \
-  80, 81, 82, 83, 84, 85, 86, 87,      \
-  88, 89, 90, 91, 92, 93, 94, 95,      \
-  32, 33,                              \
-  96, 97, 98, 99, 100,                 \
-  0, 14, 30, 31, 101}
+{ 1, 2, 3, 4, 5, 6, 7,                         /* %g1-%g7 */   \
+  29, 28, 27, 26, 25, 24,              /* %i5-%i0 */   \
+  15,                                  /* %o7 */       \
+  13, 12, 11, 10, 9, 8,                        /* %o5-%o0 */   \
+  16, 17, 18, 19, 20, 21, 22, 23,      /* %l0-%l7 */   \
+  40, 41, 42, 43, 44, 45, 46, 47,      /* %f8-%f15 */  \
+  48, 49, 50, 51, 52, 53, 54, 55,      /* %f16-%f23 */ \
+  56, 57, 58, 59, 60, 61, 62, 63,      /* %f24-%f31 */ \
+  64, 65, 66, 67, 68, 69, 70, 71,      /* %f32-%f39 */ \
+  72, 73, 74, 75, 76, 77, 78, 79,      /* %f40-%f47 */ \
+  80, 81, 82, 83, 84, 85, 86, 87,      /* %f48-%f55 */ \
+  88, 89, 90, 91, 92, 93, 94, 95,      /* %f56-%f63 */ \
+  39, 38, 37, 36, 35, 34, 33, 32,      /* %f7-%f0 */   \
+  96, 97, 98, 99,                      /* %fcc0-3 */   \
+  100, 0, 14, 30, 31, 101}             /* %icc, %g0, %o6, %i6, %i7, %sfp */
   
 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()