Rename CPU object to FullCPU

arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
cpu/static_inst.hh:
    CPU -> FullCPU

--HG--
extra : convert_revision : 2bed1ed9372ca9e33f7e391a1aa47bbc02675691

diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index c023405c8de3fb0840a62ab0e97b67abab7a0508..e9b93a895cd7938e05fb72cf93def1b43a84b4b5 100644 (file)
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -256,7 +256,7 @@ def template BasicDeclare {{
            return fault;
        }
 
-       Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+       Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
                      Trace::InstRecord *traceData)
        {
            DynInst *memAccessObj __attribute__((unused)) = dynInst;
@@ -320,7 +320,7 @@ declare {{
            return No_Fault;
        }
 
-       Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+       Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
                      Trace::InstRecord *traceData)
        {
            return No_Fault;
@@ -643,7 +643,7 @@ def template FloatingPointDeclare {{
            return fault;
        }
 
-       Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+       Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
                      Trace::InstRecord *traceData)
        {
            Fault fault = No_Fault;
@@ -701,7 +701,7 @@ def template FloatingPointDeclare {{
            return fault;
        }
 
-       Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+       Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
                      Trace::InstRecord *traceData)
        {
            Fault fault = No_Fault;
@@ -830,7 +830,7 @@ declare {{
                      Trace::InstRecord *traceData)
        { panic("attempt to execute eacomp"); }
 
-       Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+       Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
                      Trace::InstRecord *traceData)
        { panic("attempt to execute eacomp"); }
     };
@@ -852,7 +852,7 @@ declare {{
                      Trace::InstRecord *traceData)
        { panic("attempt to execute memacc"); }
 
-       Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+       Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
                      Trace::InstRecord *traceData)
        { panic("attempt to execute memacc"); }
     };
@@ -952,7 +952,7 @@ def template LoadStoreDeclare {{
            return fault;
        }
 
-       Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+       Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
                      Trace::InstRecord *traceData)
        {
            DynInst *memAccessObj = dynInst;
@@ -1019,7 +1019,7 @@ def template PrefetchDeclare {{
            return No_Fault;
        }
 
-       Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+       Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
                      Trace::InstRecord *traceData)
        {
            Addr EA;
@@ -1544,7 +1544,7 @@ declare {{
            return Unimplemented_Opcode_Fault;
        }
 
-       Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+       Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
                      Trace::InstRecord *traceData)
        {
            // don't panic if this is a misspeculated instruction
@@ -1594,7 +1594,7 @@ declare {{
            return No_Fault;
        }
 
-       Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+       Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
                      Trace::InstRecord *traceData)
        {
            if (!xc->spec_mode && !warned) {
@@ -1665,7 +1665,7 @@ declare {{
            return Unimplemented_Opcode_Fault;
        }
 
-       Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+       Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
                      Trace::InstRecord *traceData)
        {
            // don't panic if this is a misspeculated instruction

diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index 9840636e0c4d15f7c487fd05fb4a96308aba7ab5..6b78722ad4d0d146862cc62aec4171a059503c56 100644 (file)
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -33,7 +33,7 @@
 #include "targetarch/faults.hh"
 #include "base/misc.hh"
 
-class CPU;
+class FullCPU;
 class IniFile;
 
 #define TARGET_ALPHA

diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 343a3d9b7765b75f29b5402a1af36dca487b68c8..644c7dfc4dca0a54f4ff0dd7a0ee14433f9b8fb7 100644 (file)
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -43,7 +43,7 @@
 class ExecContext;
 class SpecExecContext;
 class SimpleCPU;
-class CPU;
+class FullCPU;
 class DynInst;
 class SymbolTable;
 
@@ -295,9 +295,9 @@ class StaticInst : public StaticInstBase
                           Trace::InstRecord *traceData) = 0;
 
     /**
-     * Execute this instruction under detailed CPU model.
+     * Execute this instruction under detailed FullCPU model.
      */
-    virtual Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+    virtual Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
                           Trace::InstRecord *traceData) = 0;
 
     /**