cxxrtl: Add support for memory read port reset.

diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index b312878c341acaa7a9ac4f4c53564709a6c1425f..2c93c8ad551aa5d9b06cef22cb10e61038318c1d 100644 (file)
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -1600,7 +1600,29 @@ struct CxxrtlWorker {
                        f << " = value<" << mem->width << "> {};\n";
                dec_indent();
                f << indent << "}\n";
-               if (has_enable) {
+               if (has_enable && !port.ce_over_srst) {
+                       dec_indent();
+                       f << indent << "}\n";
+               }
+               if (port.srst != State::S0) {
+                       // Synchronous reset
+                       std::vector<const RTLIL::Cell*> inlined_cells_srst;
+                       collect_sigspec_rhs(port.srst, for_debug, inlined_cells_srst);
+                       if (!inlined_cells_srst.empty())
+                               dump_inlined_cells(inlined_cells_srst);
+                       f << indent << "if (";
+                       dump_sigspec_rhs(port.srst);
+                       f << " == value<1> {1u}) {\n";
+                       inc_indent();
+                               f << indent;
+                               dump_sigspec_lhs(port.data);
+                               f << " = ";
+                               dump_const(port.srst_value);
+                               f << ";\n";
+                       dec_indent();
+                       f << indent << "}\n";
+               }
+               if (has_enable && port.ce_over_srst) {
                        dec_indent();
                        f << indent << "}\n";
                }
@@ -1608,6 +1630,24 @@ struct CxxrtlWorker {
                        dec_indent();
                        f << indent << "}\n";
                }
+               if (port.arst != State::S0) {
+                       // Asynchronous reset
+                       std::vector<const RTLIL::Cell*> inlined_cells_arst;
+                       collect_sigspec_rhs(port.arst, for_debug, inlined_cells_arst);
+                       if (!inlined_cells_arst.empty())
+                               dump_inlined_cells(inlined_cells_arst);
+                       f << indent << "if (";
+                       dump_sigspec_rhs(port.arst);
+                       f << " == value<1> {1u}) {\n";
+                       inc_indent();
+                               f << indent;
+                               dump_sigspec_lhs(port.data);
+                               f << " = ";
+                               dump_const(port.arst_value);
+                               f << ";\n";
+                       dec_indent();
+                       f << indent << "}\n";
+               }
        }
 
        void dump_mem_wrports(const Mem *mem, bool for_debug = false)