Fix tests

diff --git a/tests/arch/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys
index 313948cc5dc25b11f90bb7ed6f94860f2e3da444..70cfe81a3b726eac1f88b4af76a3f4bc268f9b9a 100644 (file)
--- a/tests/arch/xilinx/add_sub.ys
+++ b/tests/arch/xilinx/add_sub.ys
@@ -4,8 +4,8 @@ proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 14 t:LUT2
-select -assert-count 6 t:MUXCY
-select -assert-count 8 t:XORCY
-select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D
+stat
+select -assert-count 16 t:LUT2
+select -assert-count 2 t:CARRY4
+select -assert-none t:LUT2 t:CARRY4 %% t:* %D
 

diff --git a/tests/arch/xilinx/counter.ys b/tests/arch/xilinx/counter.ys
index 11c29922ec46bf14c8cec776dce0fdea385abaf8..064519ce7623dd2227d235aeac2695ac14b21b26 100644 (file)
--- a/tests/arch/xilinx/counter.ys
+++ b/tests/arch/xilinx/counter.ys
@@ -5,10 +5,9 @@ flatten
 equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-
+stat
 select -assert-count 1 t:BUFG
 select -assert-count 8 t:FDCE
 select -assert-count 1 t:INV
-select -assert-count 7 t:MUXCY
-select -assert-count 8 t:XORCY
-select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY %% t:* %D
+select -assert-count 2 t:CARRY4
+select -assert-none t:BUFG t:FDCE t:INV t:CARRY4 %% t:* %D

diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys
index 3235d5af3867f8cadfd92f9594b274c39f053c64..3cef84388f554c0192085f20f0a00af04642b3d0 100644 (file)
--- a/tests/arch/xilinx/fsm.ys
+++ b/tests/arch/xilinx/fsm.ys
@@ -9,11 +9,11 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
 
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd fsm # Constrain all select calls below inside the top module
-
+stat
 select -assert-count 1 t:BUFG
 select -assert-count 4 t:FDRE
 select -assert-count 1 t:FDSE
 select -assert-count 1 t:LUT2
-select -assert-count 3 t:LUT5
-select -assert-count 1 t:LUT6
-select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D
+select -assert-count 2 t:LUT3
+select -assert-count 4 t:LUT5
+select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT3 t:LUT5 %% t:* %D