re PR target/65979 ([SH] Wrong code is generated with stage1 compiler)

PR target/65979
* config/sh/sh.md (tstsi_t peephole2): Use gen_rtx_SET and take into
  account the case that operands[1] and operands[2] are the same register.

From-SVN: r223721

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 69289e6a8df83503439eabaf531fda2e74036a74..39d297d5a2f18fc9fb4e98c4b022265d3390719b 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2015-05-26  Oleg Endo  <olegendo@gcc.gnu.org>
+
+       PR target/65979
+       * config/sh/sh.md (tstsi_t peephole2): Use gen_rtx_SET and
+       take into account the case that operands[1] and operands[2]
+       are the same register.
+
 2015-05-26  Michael Matz  <matz@suse.de>
 
        PR middle-end/66251

diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 2d95b9c1e22d179d302cfd89c25cc493e1cecdb0..634a61250a734ea4e2ee7dab5b42e77445c7a73d 100644 (file)
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -14722,7 +14722,11 @@ label:
        || REGNO (operands[2]) == REGNO (operands[5]))"
   [(const_int 0)]
 {
-  sh_check_add_incdec_notes (emit_move_insn (operands[2], operands[3]));
+  if (REGNO (operands[1]) == REGNO (operands[2]))
+      operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));
+
+  sh_check_add_incdec_notes (emit_insn (gen_rtx_SET (operands[2],
+                                                    operands[3])));
   emit_insn (gen_tstsi_t (operands[2],
                          gen_rtx_REG (SImode, (REGNO (operands[1])))));
 })
@@ -14749,7 +14753,8 @@ label:
        || REGNO (operands[2]) == REGNO (operands[5]))"
   [(const_int 0)]
 {
-  sh_check_add_incdec_notes (emit_move_insn (operands[2], operands[3]));
+  sh_check_add_incdec_notes (emit_insn (gen_rtx_SET (operands[2],
+                                                    operands[3])));
   emit_insn (gen_tstsi_t (operands[2],
                          gen_rtx_REG (SImode, (REGNO (operands[1])))));
 })