The o3 cpu relies upon instructions that suspend a thread context being
flagged as "IsQuiesce". If they are not, unpredictable behavior can occur.
This patch fixes that for the x86 ISA.
}}, IsNonSpeculative);
0x01: m5quiesce({{
PseudoInst::quiesce(xc->tcBase());
- }}, IsNonSpeculative);
+ }}, IsNonSpeculative, IsQuiesce);
0x02: m5quiesceNs({{
PseudoInst::quiesceNs(xc->tcBase(), Rdi);
- }}, IsNonSpeculative);
+ }}, IsNonSpeculative, IsQuiesce);
0x03: m5quiesceCycle({{
PseudoInst::quiesceCycles(xc->tcBase(), Rdi);
- }}, IsNonSpeculative);
+ }}, IsNonSpeculative, IsQuiesce);
0x04: m5quiesceTime({{
Rax = PseudoInst::quiesceTime(xc->tcBase());
}}, IsNonSpeculative);
MicroHalt(ExtMachInst _machInst, const char * instMnem,
uint64_t setFlags) :
X86MicroopBase(_machInst, "halt", instMnem,
- setFlags | (ULL(1) << StaticInst::IsNonSpeculative),
+ setFlags | (ULL(1) << StaticInst::IsNonSpeculative) |
+ (ULL(1) << StaticInst::IsQuiesce),
No_OpClass)
{
}