+Tue Nov 24 14:13:10 1998 Andrew Cagney <cagney@chook>
+
+ * breakpoint.c (memory_breakpoint_size): Delete global.
+ (read_memory_nobpt): Determine real breakpoint address and size
+ using BREAKPOINT_FROM_PC.
+
+ * defs.h (breakpoint_from_pc_fn): BREAKPOINT_FROM_PC function
+ template.
+ * target.h, mem-break.c (memory_breakpoint_from_pc):
+ Rewrite. Always define. Return NULL when memory breakpoints are
+ not supported.
+ (memory_insert_breakpoint, memory_remove_breakpoint): Call
+ BREAKPOINT_FROM_PC.
+ * target.h (BREAKPOINT_FROM_PC): Provide default.
+ * gdbint.texinfo (BREAKPOINT_FROM_PC): Document.
+
+ * config/rs6000/tm-rs6000.h (BREAKPOINT): Delete macro.
+ (BREAKPOINT_FROM_PC): Define.
+ ({BIG,LITTLE}_BREAKPOINT): Move macros from here.
+ * rs6000-tdep.c: To here.
+ (rs6000_breakpoint_from_pc): New function.
+
+ * config/mn10300/tm-mn10300.h (BREAKPOINT): Delete macro.
+ (BREAKPOINT_FROM_PC): Define, call.
+ * mn10300-tdep.c (mn10300_breakpoint_from_pc): New function.
+
+ * config/mips/tm-mips.h ({BIG,LITTLE}_BREAKPOINT,
+ IDT_{BIG,LITTLE}_BREAKPOINT, PMON_{BIG,LITTLE}_BREAKPOINT,
+ MIPS16_{BIG,LITTLE}_BREAKPOINT): Move macros from here.
+ * mips-tdep.c: To here.
+start-sanitize-sky
+ * txvu-tdep.c (core_break_insn): Delete variable.
+ (txvu_insert_breakpoint): Update, use BREAKPOINT_FROM_PC.
+end-sanitize-sky
+
+ * config/arm/tm-arm.h ({BIG,LITTLE}_BREAKPOINT): Delete macros.
+ ({ARM,THUMB}_{BE,LE}_BREAKPOINT): Move macros from here.
+ * arm-tdep.c: To here.
+
+ * remote-array.c (memory_breakpoint_size): Delete variable.
+ (array_insert_breakpoint): Obtain breakpoint size using
+ BREAKPOINT_FROM_PC.
+ * remote-st.c (memory_breakpoint_size, st2000_insert_breakpoint):
+ Ditto.
+ * remote-os9k.c (memory_breakpoint_size,
+ rombug_insert_breakpoint): Ditto.
+ * remote-e7000.c (memory_breakpoint_size): Ditto.
+
Mon Nov 23 11:38:40 1998 Michael Snyder <msnyder@cleaver.cygnus.com>
* symfile.c (deduce_language_from_filename): rewrite so as to
#define BIG_ENDIAN 4321
-/* Old-style breakpoint macros.
- The IDT board uses an unusual breakpoint value, and sometimes gets
- confused when it sees the usual MIPS breakpoint instruction. */
-
-#define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
-#define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
-#define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
-#define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
-#define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
-#define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
-#define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
-#define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
-
/* BREAKPOINT_FROM_PC uses the program counter value to determine whether a
16- or 32-bit breakpoint should be used. It returns a pointer
to a string of bytes that encode a breakpoint instruction, stores
point to the actual memory location where the breakpoint should be
inserted. */
-unsigned char *mips_breakpoint_from_pc PARAMS ((CORE_ADDR *pcptr, int *lenptr));
+extern breakpoint_from_pc_fn mips_breakpoint_from_pc;
#define BREAKPOINT_FROM_PC(pcptr, lenptr) mips_breakpoint_from_pc(pcptr, lenptr)
/* Amount PC must be decremented by after a breakpoint.
/* Pseudo register that contains true address of executing stack frame */
#define FP_REGNUM 31
-/* The breakpoint instruction must be the same size as the smallest
- instruction in the instruction set.
-
- The Matsushita mn10x00 processors have single byte instructions
- so we need a single byte breakpoint. Matsushita hasn't defined
- one, so we defined it ourselves. */
-#define BREAKPOINT {0xff}
+/* BREAKPOINT_FROM_PC uses the program counter value to determine the
+ breakpoint that should be used */
+extern breakpoint_from_pc_fn mn10300_breakpoint_from_pc;
+#define BREAKPOINT_FROM_PC(pcptr, lenptr) mn10300_breakpoint_from_pc (pcptr, lenptr)
#define FUNCTION_START_OFFSET 0
@item LITTLE_BREAKPOINT
Similar to BREAKPOINT, but used for bi-endian targets.
+@item REMOTE_BREAKPOINT
+@item LITTLE_REMOTE_BREAKPOINT
+@item BIG_REMOTE_BREAKPOINT
+Similar to BREAKPOINT, but used for remote targets.
+
+@item BREAKPOINT_FROM_PC (pcptr, lenptr)
+
+Use the program counter to determine the contents and size of a
+breakpoint instruction. It returns a pointer to a string of bytes that
+encode a breakpoint instruction, stores the length of the string to
+*lenptr, and adjusts pc (if necessary) to point to the actual memory
+location where the breakpoint should be inserted.
+
+Although it is common to use a trap instruction for a breakpoint, it's
+not required; for instance, the bit pattern could be an invalid
+instruction. The breakpoint must be no longer than the shortest
+instruction of the architecture.
+
+Replaces all the other BREAKPOINTs.
+
@item CALL_DUMMY
valops.c
@item CALL_DUMMY_LOCATION
return (TYPE_NFIELDS (type) > 1 || TYPE_LENGTH (type) > 8);
}
+/* The breakpoint instruction must be the same size as the smallest
+ instruction in the instruction set.
+
+ The Matsushita mn10x00 processors have single byte instructions
+ so we need a single byte breakpoint. Matsushita hasn't defined
+ one, so we defined it ourselves. */
+
+unsigned char *
+mn10300_breakpoint_from_pc (bp_addr, bp_size)
+ CORE_ADDR *bp_addr;
+ int *bp_size;
+{
+ static char breakpoint[] = {0xff};
+ *bp_size = 1;
+ return breakpoint;
+}
+
/* Fix fi->frame if it's bogus at this point. This is a helper
function for mn10300_analyze_prologue. */
/* Remote debugging interface for Array Tech RAID controller..
- Copyright 90, 91, 92, 93, 94, 1995 Free Software Foundation, Inc.
+ Copyright 90, 91, 92, 93, 94, 1995, 1998 Free Software Foundation, Inc.
Contributed by Cygnus Support. Written by Rob Savoye for Cygnus.
This module talks to a debug monitor called 'MONITOR', which
#define MAX_ARRAY_BREAKPOINTS 16
-extern int memory_breakpoint_size;
static CORE_ADDR breakaddr[MAX_ARRAY_BREAKPOINTS] = {0};
/*
char *shadow;
{
int i;
+ int bp_size = 0;
+ int bp_addr = addr;
debuglogs (1, "array_insert_breakpoint() addr = 0x%x", addr);
+ BREAKPOINT_FROM_PC (&bp_addr, &bp_size);
for (i = 0; i <= MAX_ARRAY_BREAKPOINTS; i++) {
if (breakaddr[i] == 0) {
breakaddr[i] = addr;
if (sr_get_debug() > 4)
printf ("Breakpoint at %x\n", addr);
- array_read_inferior_memory(addr, shadow, memory_breakpoint_size);
+ array_read_inferior_memory (bp_addr, shadow, bp_size);
printf_monitor("b 0x%x\n", addr);
expect_prompt(1);
return 0;
#define MAX_MONITOR_BREAKPOINTS 16
-extern int memory_breakpoint_size;
static CORE_ADDR breakaddr[MAX_MONITOR_BREAKPOINTS] = {0};
static int
char *shadow;
{
int i;
+ CORE_ADDR bp_addr = addr;
+ int bp_size = 0;
if (monitor_log)
fprintf (log_file, "\nIn Insert_breakpoint (addr=%x)\n", addr);
+ BREAKPOINT_FROM_PC (&bp_addr, &bp_size);
for (i = 0; i <= MAX_MONITOR_BREAKPOINTS; i++)
if (breakaddr[i] == 0)
breakaddr[i] = addr;
if (sr_get_debug())
printf ("Breakpoint at %x\n", addr);
- rombug_read_inferior_memory(addr, shadow, memory_breakpoint_size);
+ rombug_read_inferior_memory (bp_addr, shadow, bp_size);
printf_monitor(SET_BREAK_CMD, addr);
is_trace_mode = 0;
expect_prompt(1);
#define MAX_STDEBUG_BREAKPOINTS 16
-extern int memory_breakpoint_size;
static CORE_ADDR breakaddr[MAX_STDEBUG_BREAKPOINTS] = {0};
static int
char *shadow;
{
int i;
+ CORE_ADDR bp_addr = addr;
+ int bp_size = 0;
+
+ BREAKPOINT_FROM_PC (&bp_addr, &bp_size);
for (i = 0; i <= MAX_STDEBUG_BREAKPOINTS; i++)
if (breakaddr[i] == 0)
{
breakaddr[i] = addr;
- st2000_read_inferior_memory(addr, shadow, memory_breakpoint_size);
+ st2000_read_inferior_memory (bp_addr, shadow, bp_size);
printf_stdebug("BR %x H\r", addr);
expect_prompt(1);
return 0;
}
+/* Sequence of bytes for breakpoint instruction. */
+
+#define BIG_BREAKPOINT { 0x7d, 0x82, 0x10, 0x08 }
+#define LITTLE_BREAKPOINT { 0x08, 0x10, 0x82, 0x7d }
+
+unsigned char *
+rs6000_breakpoint_from_pc (bp_addr, bp_size)
+ CORE_ADDR *bp_addr;
+ int *bp_size;
+{
+ static unsigned char *big_breakpoint = BIG_BREAKPOINT;
+ static unsigned char *little_breakpoint = LITTLE_BREAKPOINT;
+ *bp_size = 4;
+ if (TARGET_BYTE_ORDER == BIG_ENDIAN)
+ return big_breakpoint;
+ else
+ return little_breakpoint;
+}
+
/* AIX does not support PT_STEP. Simulate it. */
projects / binutils-gdb.git / commitdiff