extract_rdff: Add initvals parameter.
authorMarcelina Kościelnicka <mwk@0x04.net>
Sun, 23 May 2021 16:29:44 +0000 (18:29 +0200)
committerMarcelina Kościelnicka <mwk@0x04.net>
Sun, 23 May 2021 20:05:26 +0000 (22:05 +0200)
This is not used yet, but will be needed when read port reset/initial
value support lands.

kernel/mem.cc
kernel/mem.h
passes/memory/memory_map.cc
passes/memory/memory_nordff.cc

index 7d20833e5436a2892cac742dee0c8922e88d7ee3..4c3b333c1c378e1cd50a9ae38060005bc129ab99 100644 (file)
@@ -445,7 +445,7 @@ std::vector<Mem> Mem::get_selected_memories(Module *module) {
        return res;
 }
 
-Cell *Mem::extract_rdff(int idx) {
+Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) {
        MemRd &port = rd_ports[idx];
 
        if (!port.clk_enable)
index f5c7b641ffada3bde419d641275d977d2f6e4ca8..a2af6a183c6c828551bb980f18b561e8e7b9b9c9 100644 (file)
@@ -21,6 +21,7 @@
 #define MEM_H
 
 #include "kernel/yosys.h"
+#include "kernel/ffinit.h"
 
 YOSYS_NAMESPACE_BEGIN
 
@@ -70,7 +71,7 @@ struct Mem {
        Const get_init_data() const;
        static std::vector<Mem> get_all_memories(Module *module);
        static std::vector<Mem> get_selected_memories(Module *module);
-       Cell *extract_rdff(int idx);
+       Cell *extract_rdff(int idx, FfInitVals *initvals);
        Mem(Module *module, IdString memid, int width, int start_offset, int size) : module(module), memid(memid), packed(false), mem(nullptr), cell(nullptr), width(width), start_offset(start_offset), size(size) {}
 };
 
index 032b8fbbdf753af4029a1e1708d0ff33164c1381..57863c0b677c0b6dcabd0cb31724aa3e666c3443 100644 (file)
@@ -34,10 +34,12 @@ struct MemoryMapWorker
 
        RTLIL::Design *design;
        RTLIL::Module *module;
+       SigMap sigmap;
+       FfInitVals initvals;
 
        std::map<std::pair<RTLIL::SigSpec, RTLIL::SigSpec>, RTLIL::SigBit> decoder_cache;
 
-       MemoryMapWorker(RTLIL::Design *design, RTLIL::Module *module) : design(design), module(module) {}
+       MemoryMapWorker(RTLIL::Design *design, RTLIL::Module *module) : design(design), module(module), sigmap(module), initvals(&sigmap, module) {}
 
        std::string map_case(std::string value) const
        {
@@ -228,7 +230,7 @@ struct MemoryMapWorker
                for (int i = 0; i < GetSize(mem.rd_ports); i++)
                {
                        auto &port = mem.rd_ports[i];
-                       if (mem.extract_rdff(i))
+                       if (mem.extract_rdff(i, &initvals))
                                count_dff++;
                        RTLIL::SigSpec rd_addr = port.addr;
                        rd_addr.extend_u0(abits, false);
index bb853c483ebf6c2e3c38598c1a37aabe3abc9f1d..665efceb202bb754b0e86128c74e836ec28fb1ae 100644 (file)
@@ -51,15 +51,19 @@ struct MemoryNordffPass : public Pass {
                extra_args(args, argidx, design);
 
                for (auto module : design->selected_modules())
-               for (auto &mem : Mem::get_selected_memories(module))
                {
-                       bool changed = false;
-                       for (int i = 0; i < GetSize(mem.rd_ports); i++)
-                               if (mem.extract_rdff(i))
-                                       changed = true;
+                       SigMap sigmap(module);
+                       FfInitVals initvals(&sigmap, module);
+                       for (auto &mem : Mem::get_selected_memories(module))
+                       {
+                               bool changed = false;
+                               for (int i = 0; i < GetSize(mem.rd_ports); i++)
+                                       if (mem.extract_rdff(i, &initvals))
+                                               changed = true;
 
-                       if (changed)
-                               mem.emit();
+                               if (changed)
+                                       mem.emit();
+                       }
                }
        }
 } MemoryNordffPass;