freedreno/ir3: fix bogus register footprint with tess/gs

When we have a tess or gs stage, VS outputs aren't normal varyings, so
regid is r63.x.. we shouldn't extend our registerfootprint to 64!

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>

diff --git a/src/freedreno/ir3/ir3_shader.c b/src/freedreno/ir3/ir3_shader.c
index c66330147e0957715b1d0410e3637981933bacc5..5ea6ba9390212bb6084d2f16beba0fd6069ede65 100644 (file)
--- a/src/freedreno/ir3/ir3_shader.c
+++ b/src/freedreno/ir3/ir3_shader.c
@@ -96,6 +96,9 @@ fixup_regfootprint(struct ir3_shader_variant *v, uint32_t gpu_id)
        }
 
        for (i = 0; i < v->outputs_count; i++) {
+               /* for ex, VS shaders with tess don't have normal varying outs: */
+               if (!VALIDREG(v->outputs[i].regid))
+                       continue;
                int32_t regid = v->outputs[i].regid + 3;
                if (v->outputs[i].half) {
                        if (gpu_id < 500) {