whoops copy sign over on zero

diff --git a/openpower/isafunctions/double2single.mdwn b/openpower/isafunctions/double2single.mdwn
index 218beecd6006aea2b4b48d765328b6c3100441cf..bda22763e4fd3e0ea22fe1e41e3d2b778279f0cb 100644 (file)
--- a/openpower/isafunctions/double2single.mdwn
+++ b/openpower/isafunctions/double2single.mdwn
@@ -114,11 +114,11 @@ Round to Single-Precision instruction.
 
         if mode = 'zero_operand':
             # Zero Operand
+            result[0]  <- FR[0] # copy sign, the rest is zero
             # TODO, FPSCR
             #FPSCR[FR] <- 0b00
             #FPSCR[FI] <- 0b00
             #FPSCR[FPRF] <- '+ zero'
-            result <- [0] * 64
 
         if mode = 'disabled_exp_underflow':
             if sign = 1 then frac[0:63] <- ¬frac[0:63] + 1

diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index 6285a6690367e076d6268e3fe2f53b8e5b0180bd..83812637b92662a2558e55f9b980ad20dc49fa2f 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -241,6 +241,22 @@ class DecoderTestCase(FHDLTestCase):
             sim = self.run_tst_program(program, initial_fprs=fprs)
             self.assertEqual(sim.fpr(3), SelectableInt(0x3d9d8b31c0000000, 64))
 
+    def test_fp_muls4(self):
+        """>>> lst = ["fmuls 3, 1, 2",
+                     ]
+        """
+        lst = ["fmuls 3, 1, 2", #
+                     ]
+
+        fprs = [0] * 32
+        fprs[1] = 0xbe724e2000000000 # negative number
+        fprs[2] = 0x0                # times zero
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_fprs=fprs)
+            # result should be -ve zero not +ve zero
+            self.assertEqual(sim.fpr(3), SelectableInt(0x8000000000000000, 64))
+
     def test_fp_mul(self):
         """>>> lst = ["fmul 3, 1, 2",
                      ]