}
else if (!cachePort->isCpuSide)
{
+ assert(cachePort->cache->doMasterRequest());
//MSHR
pkt = cachePort->cache->getPacket();
MSHR* mshr = (MSHR*) pkt->senderState;
}
else
{
+ assert(cachePort->cache->doSlaveRequest());
//CSHR
pkt = cachePort->cache->getCoherencePacket();
bool success = cachePort->sendTiming(pkt);
*/
void setMasterRequest(RequestCause cause, Tick time)
{
- if (!doMasterRequest() && memSidePort->drainList.empty())
+ if (!doMasterRequest() && !memSidePort->waitingOnRetry)
{
BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
reqCpu->schedule(time);