(dect): Rewrite pattern so that it can be combined.

From-SVN: r13307

diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 07bc69afdbe33820527d05d54cffa84495d9a405..6c75623ab0bb965458897bd34c3d4209ba545e9f 100644 (file)
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -222,10 +222,6 @@
   ""
   "movt        %0")
 
-;; ??? This combiner pattern does not work, because combine does not combine
-;; instructions that set a hard register when SMALL_REGISTER_CLASSES is
-;; defined.  Perhaps use a pseudo-reg for the T bit?
-
 (define_insn ""
   [(set (reg:SI 18)
        (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
@@ -2108,17 +2104,10 @@
 ;; Misc insns
 ;; ------------------------------------------------------------------------
 
-;; ??? This combiner pattern does not work, because combine does not combine
-;; instructions that set a hard register when SMALL_REGISTER_CLASSES is
-;; defined.  Perhaps use a pseudo-reg for the T bit?
-
 (define_insn "dect"
-  [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-                  (plus:SI (match_dup 0)
-                           (const_int -1)))
-             (set (reg:SI 18)
-                  (eq:SI (plus:SI (match_dup 0) (const_int -1))
-                         (const_int 0)))])]
+  [(set (reg:SI 18)
+       (eq:SI (match_operand:SI 0 "arith_reg_operand" "+r") (const_int 1)))
+   (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
   "TARGET_SH2"
   "dt  %0")