Towards DRAM support in Xilinx flow

diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 5253e129dcfa45018ff49fd57da9fc811e1dedac..76a0cd7425f39a9dbfc24bcf6fdec45f4a3084c3 100644 (file)
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -27,5 +27,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_init_18.vh))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_init_16.vh))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_bb.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams.txt))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_bb.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
 

diff --git a/techlibs/xilinx/drams.txt b/techlibs/xilinx/drams.txt
new file mode 100644 (file)
index 0000000..84175b2
--- /dev/null
+++ b/techlibs/xilinx/drams.txt
@@ -0,0 +1,17 @@
+
+bram $__XILINX_RAM32X1D
+  init 1
+  abits 5
+  dbits 1
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 1
+  transp 0 0
+  clocks 0 1
+  clkpol 0 2
+endbram
+
+match $__XILINX_RAM32X1D
+endmatch
+

diff --git a/techlibs/xilinx/drams_bb.v b/techlibs/xilinx/drams_bb.v
new file mode 100644 (file)
index 0000000..f3169ab
--- /dev/null
+++ b/techlibs/xilinx/drams_bb.v
@@ -0,0 +1,11 @@
+
+module RAM32X1D (
+       output DPO, SPO,
+       input  A0, A1, A2, A3, A4, D,
+       input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4,
+       input  WCLK, WE
+);
+       parameter INIT = 32'h0;
+       parameter IS_WCLK_INVERTED = 1'b0;
+endmodule
+

diff --git a/techlibs/xilinx/drams_map.v b/techlibs/xilinx/drams_map.v
new file mode 100644 (file)
index 0000000..c082515
--- /dev/null
+++ b/techlibs/xilinx/drams_map.v
@@ -0,0 +1,35 @@
+
+module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+       parameter [31:0] INIT = 32'bx;
+       parameter CLKPOL2 = 1;
+       input CLK1;
+
+       input [4:0] A1ADDR;
+       output A1DATA;
+
+       input [4:0] B1ADDR;
+       input B1DATA;
+       input B1EN;
+
+       RAM32X1D #(
+               .INIT(INIT),
+               .IS_WCLK_INVERTED(!CLKPOL2)
+       ) _TECHMAP_REPLACE_ (
+               .DPRA0(A1ADDR[0]),
+               .DPRA1(A1ADDR[1]),
+               .DPRA2(A1ADDR[2]),
+               .DPRA3(A1ADDR[3]),
+               .DPRA4(A1ADDR[4]),
+               .DPO(A1DATA),
+
+               .A0(B1ADDR[0]),
+               .A1(B1ADDR[1]),
+               .A2(B1ADDR[2]),
+               .A3(B1ADDR[3]),
+               .A4(B1ADDR[4]),
+               .D(B1DATA),
+               .WCLK(CLK1),
+               .WE(B1EN)
+       );
+endmodule
+

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index aac8e9123ac209d6b0a06739b07c7d6d7825b024..0e2fdac7377bc21defc0198b4c2af8567aeb9320 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -70,6 +70,7 @@ struct SynthXilinxPass : public Pass {
                log("    begin:\n");
                log("        read_verilog -lib +/xilinx/cells_sim.v\n");
                log("        read_verilog -lib +/xilinx/brams_bb.v\n");
+               log("        read_verilog -lib +/xilinx/drams_bb.v\n");
                log("        hierarchy -check -top <top>\n");
                log("\n");
                log("    flatten:     (only if -flatten)\n");
@@ -84,6 +85,10 @@ struct SynthXilinxPass : public Pass {
                log("        memory_bram -rules +/xilinx/brams.txt\n");
                log("        techmap -map +/xilinx/brams_map.v\n");
                log("\n");
+               log("    dram:\n");
+               log("        memory_bram -rules +/xilinx/drams.txt\n");
+               log("        techmap -map +/xilinx/drams_map.v\n");
+               log("\n");
                log("    fine:\n");
                log("        opt -fast -full\n");
                log("        memory_map\n");
@@ -160,6 +165,7 @@ struct SynthXilinxPass : public Pass {
                {
                        Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v");
                        Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v");
+                       Pass::call(design, "read_verilog -lib +/xilinx/drams_bb.v");
                        Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str()));
                }
 
@@ -181,6 +187,12 @@ struct SynthXilinxPass : public Pass {
                        Pass::call(design, "techmap -map +/xilinx/brams_map.v");
                }
 
+               if (check_label(active, run_from, run_to, "dram"))
+               {
+                       Pass::call(design, "memory_bram -rules +/xilinx/drams.txt");
+                       Pass::call(design, "techmap -map +/xilinx/drams_map.v");
+               }
+
                if (check_label(active, run_from, run_to, "fine"))
                {
                        Pass::call(design, "opt -fast -full");