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missed one sorting order in test_pysvp64dis.py
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 20 Sep 2022 11:13:43 +0000 (12:13 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 20 Sep 2022 11:13:43 +0000 (12:13 +0100)
src/openpower/sv/trans/test_pysvp64dis.py patch | blob | history

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index c44d25112aae9d553a6b92c871e74b6012d78bd3..4b751118b65dbcc2ea5ceaadaa421746afded535 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -288,9 +288,9 @@ class SVSTATETestCase(unittest.TestCase):
                     "sv.bc/all/lru/sl/slu/snz/vsi 12,*1,0xc",
                     "sv.bc/all/lru/sl/slu/snz/vsb 12,*1,0xc",
                     "sv.bc/all/lru/sl/slu/snz/vsbi 12,*1,0xc",
-                    "sv.bc/all/ctr/lru/snz/sl/slu 12,*1,0xc",
-                    "sv.bc/all/cti/sl/slu/lru/snz 12,*1,0xc",
-                    "sv.bc/all/ctr/sl/slu/lru/snz/vsb 12,*1,0xc",
+                    "sv.bc/all/ctr/lru/sl/slu/snz 12,*1,0xc",
+                    "sv.bc/all/cti/lru/sl/slu/snz 12,*1,0xc",
+                    "sv.bc/all/ctr/lru/sl/slu/snz/vsb 12,*1,0xc",
                         ]
         self._do_tst(expected)