arch-arm: ArmISA::clear, inval TLB cached miscregs

ArmISA::clear resets the value of the architecture registers. Some of
these are cached in ArmTLB, including SCTLR. This patch invalidates the
cached copies on clear; this fixes a bug when resetting CPU cores by which
the cached SCTLR was used and SCTLR.M was set, resulting in non-arch
compliant reset behaviour and a PA being treated as a VA on translation.

Change-Id: I8d4eeeaf807325bd7b300a7a317abfa40ad23c87
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25466
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index f6faf5b042e524feb4e1758563eaf040cb72c4a7..205f82f2d78654fbd5e4695e9fa1d49a8e3a462f 100644 (file)
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -119,6 +119,15 @@ ISA::params() const
     return dynamic_cast<const Params *>(_params);
 }
 
+void
+ISA::clear(ThreadContext *tc)
+{
+    clear();
+    // Invalidate cached copies of miscregs in the TLBs
+    getITBPtr(tc)->invalidateMiscReg();
+    getDTBPtr(tc)->invalidateMiscReg();
+}
+
 void
 ISA::clear()
 {

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 89be0158acfe99413d9174995951bff67c6efd66..736c395a762a30292a99ab6cf0879b9feac347ec 100644 (file)
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -463,7 +463,7 @@ namespace ArmISA
         }
 
       public:
-        void clear(ThreadContext *tc) { clear(); }
+        void clear(ThreadContext *tc);
 
       protected:
         void clear();