targets: fix MiniSoC

diff --git a/targets/kc705.py b/targets/kc705.py
index 6f278399a909554d0706835a9b57577ff1c20a2d..ddbe406f7af5ccfa73b8b91a191f0d7d9c49c9a2 100644 (file)
--- a/targets/kc705.py
+++ b/targets/kc705.py
@@ -131,6 +131,6 @@ class MiniSoC(BaseSoC):
                self.submodules.ethphy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth"))
                self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
                self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
-               self.add_cpu_memory_region("ethmac_mem", self.mem_map["ethmac"]+0x80000000, 0x2000)
+               self.add_memory_region("ethmac_mem", self.mem_map["ethmac"]+0x80000000, 0x2000)
 
 default_subtarget = BaseSoC

diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index dc4d58cb29437b9eddec7bdddbbdef820d3cf39c..a6dab0a6f21e24b6f20bd9bab43f234b7a05aaa4 100644 (file)
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -101,7 +101,7 @@ class MiniSoC(BaseSoC):
                self.submodules.ethphy = LiteEthPHYMII(platform.request("eth_clocks"), platform.request("eth"))
                self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
                self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
-               self.add_cpu_memory_region("ethmac_mem", self.mem_map["ethmac"]+0x80000000, 0x2000)
+               self.add_memory_region("ethmac_mem", self.mem_map["ethmac"]+0x80000000, 0x2000)
 
 def get_vga_dvi(platform):
        try: