vexriscv/core: fix min variant

diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 1edcc3f7bba90c376b50aef7d8a4fb225a7ecf6e..3700bf44c990ae195efd28a4d72be4e30176ca04 100644 (file)
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -155,8 +155,8 @@ class VexRiscv(Module, AutoCSR):
             "std_debug":  "VexRiscv_Debug.v",
             "lite":       "VexRiscv_Lite.v",
             "lite_debug": "VexRiscv_LiteDebug.v",
-            "min":        "VexRiscv_Lite.v",
-            "min_debug":  "VexRiscv_LiteDebug.v",
+            "min":        "VexRiscv_Min.v",
+            "min_debug":  "VexRiscv_MinDebug.v",
         }
         cpu_filename = verilog_variants[variant]
         vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")