arm: change MISCREG_L2ERRSR to warn not fail

Some newer binaries compiled for Versatile Express TC2 contain access
to implementation specific L2MERRSR registers. This causes an infinite
loop of undefined exceptions. This patch changes the behavior to "warn
not fail" to keep the workloads going.

diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 313ac18f96b91b651337bae6408357b2b4cfb630..4c950a6439a4d1b2c07291f48d76f4c8e8396076 100644 (file)
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -770,7 +770,7 @@ bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS] = {
     // MISCREG_CPUMERRSR
     bitset<NUM_MISCREG_INFOS>(string("1111111111000000000")),
     // MISCREG_L2MERRSR
-    bitset<NUM_MISCREG_INFOS>(string("1111111111000000000")),
+    bitset<NUM_MISCREG_INFOS>(string("1111111111000000010")),
 
     // AArch64 registers (Op0=2)
     // MISCREG_MDCCINT_EL1
@@ -1330,7 +1330,7 @@ bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS] = {
     // MISCREG_CPUMERRSR_EL1
     bitset<NUM_MISCREG_INFOS>(string("1111111111000000001")),
     // MISCREG_L2MERRSR_EL1
-    bitset<NUM_MISCREG_INFOS>(string("1111111111000000001")),
+    bitset<NUM_MISCREG_INFOS>(string("1111111111000000010")),
     // MISCREG_CBAR_EL1
     bitset<NUM_MISCREG_INFOS>(string("0101010101000000001")),