gen/fhdl/verilog: explicitly define input/output/inout wires.

When integrating designs which set `default_nettype none, the top also needs
to explicitly define the type of the signals.

diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index f515dbfb2848779123207c080a1ccc4584def775..98a732707cb4ac8af4899cf23e92d3159f35e619 100644 (file)
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -236,17 +236,17 @@ def _printheader(f, ios, name, ns, attr_translate,
         sig.type = "wire"
         if sig in inouts:
             sig.direction = "inout"
-            r += "\tinout " + _printsig(ns, sig)
+            r += "\tinout wire " + _printsig(ns, sig)
         elif sig in targets:
             sig.direction = "output"
             if sig in wires:
-                r += "\toutput " + _printsig(ns, sig)
+                r += "\toutput wire " + _printsig(ns, sig)
             else:
                 sig.type = "reg"
                 r += "\toutput reg " + _printsig(ns, sig)
         else:
             sig.direction = "input"
-            r += "\tinput " + _printsig(ns, sig)
+            r += "\tinput wire " + _printsig(ns, sig)
     r += "\n);\n\n"
     for sig in sorted(sigs - ios, key=lambda x: x.duid):
         attr = _printattr(sig.attr, attr_translate)