Add tests for some common techmap files.
authorMarcelina Kościelnicka <mwk@0x04.net>
Tue, 23 Feb 2021 20:23:26 +0000 (21:23 +0100)
committerMarcelina Kościelnicka <mwk@0x04.net>
Wed, 24 Feb 2021 00:07:34 +0000 (01:07 +0100)
tests/techmap/adff2dff.ys [new file with mode: 0644]
tests/techmap/dff2ff.ys [new file with mode: 0644]
tests/techmap/pmux2mux.ys [new file with mode: 0644]

diff --git a/tests/techmap/adff2dff.ys b/tests/techmap/adff2dff.ys
new file mode 100644 (file)
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--- /dev/null
@@ -0,0 +1,19 @@
+read_verilog -icells << EOT
+module top(...);
+
+input [1:0] D;
+input C, R;
+output [1:0] Q;
+
+always @(posedge C, posedge R)
+  if (R)
+    Q <= 0;
+  else
+    Q <= D;
+
+endmodule
+EOT
+
+proc
+
+equiv_opt -async2sync techmap -map +/adff2dff.v
diff --git a/tests/techmap/dff2ff.ys b/tests/techmap/dff2ff.ys
new file mode 100644 (file)
index 0000000..5adf14b
--- /dev/null
@@ -0,0 +1,16 @@
+read_verilog -icells << EOT
+module top(...);
+
+input [1:0] D;
+input C;
+output [1:0] Q;
+
+always @(posedge C)
+  Q <= D;
+
+endmodule
+EOT
+
+proc
+
+equiv_opt techmap -map +/dff2ff.v
diff --git a/tests/techmap/pmux2mux.ys b/tests/techmap/pmux2mux.ys
new file mode 100644 (file)
index 0000000..1714a6b
--- /dev/null
@@ -0,0 +1,15 @@
+read_verilog -icells << EOT
+module top(...);
+
+input [3:0] A;
+input [3:0] B0;
+input [3:0] B1;
+input [1:0] S;
+output [3:0] O;
+
+\$pmux #(.WIDTH(4), .S_WIDTH(2)) pm (.A(A), .B({B1, B0}), .S(S), .Y(O));
+
+endmodule
+EOT
+
+equiv_opt techmap -map +/pmux2mux.v