radeon/vcn: enable rate control for hevc encoding

Set cu_qp_delta_enable_flag on when rate control is enabled, and set it
off when rate control is disabled (e.g. constant qp).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673
Cc: mesa-stable@lists.freedesktop.org
V2: fix typo and add bugzilla info

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 05f9531b249ce4bc46fae35e5b67ae7d87aa4f44..c125fe49d554eb33e579afaad005479fa924de32 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -490,7 +490,13 @@ static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
        radeon_enc_code_se(enc, 0x0);
        radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
        radeon_enc_code_fixed_bits(enc, 0x0, 1);
-       radeon_enc_code_fixed_bits(enc, 0x0, 1);
+       if (enc->enc_pic.rc_session_init.rate_control_method ==
+               RENCODE_RATE_CONTROL_METHOD_NONE)
+               radeon_enc_code_fixed_bits(enc, 0x0, 1);
+       else {
+               radeon_enc_code_fixed_bits(enc, 0x1, 1);
+               radeon_enc_code_ue(enc, 0x0);
+       }
        radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
        radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
        radeon_enc_code_fixed_bits(enc, 0x0, 1);