update

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 18ae7b4cdfc942e2a3577a768f3af67d2ba4f203..b72a5f61b996ea2c164f10019a76edc707a0d29f 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -209,7 +209,8 @@
    \item SIMD ALU(s) primarily unchanged\vspace{6pt}
    \item Predication is added to each SIMD element\vspace{6pt}
    \item Predication bits sent in groups to the ALU\vspace{6pt}
-   \item End of Vector enables (additional) predication\vspace{10pt}
+   \item End of Vector enables (additional) predication\\
+            (completely nullifies need for end-case code)
   \end{itemize}
   Considerations:\vspace{4pt}
    \begin{itemize}