i965/blorp: Enable blorp blits on Gen7.

Gen7 support for blorp (blits using the render bath) now works for
non-MSAA purposes.  This patch enables it.

Since blorp operations re-use the logic for HiZ ops, this required
adding a case to the switch statement in gen7_blorp_emit_wm_config(),
to allow for the case where no HiZ op is being performed.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 47452b8d64df6748a8898a80e70a5b2f21f09de9..10d94a681d753ef213ffc04dc6a774ff699045f6 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -187,8 +187,8 @@ brw_blorp_framebuffer(struct intel_context *intel,
                       GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
                       GLbitfield mask, GLenum filter)
 {
-   /* BLORP is only supported on Gen6.  TODO: implement on Gen7. */
-   if (intel->gen != 6)
+   /* BLORP is not supported before Gen6. */
+   if (intel->gen < 6)
       return mask;
 
    static GLbitfield buffer_bits[] = {

diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 04548bf63b89baedf9ff5d879f3ee2c0e0aecf42..9e1aa4b8d94e88fcfeab4aefde00296a0e63c940 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -416,6 +416,8 @@ gen7_blorp_emit_wm_config(struct brw_context *brw,
    case GEN6_HIZ_OP_HIZ_RESOLVE:
       dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
       break;
+   case GEN6_HIZ_OP_NONE:
+      break;
    default:
       assert(0);
       break;