Only pack out registers if \init is zero or x; then remove \init from PREG

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 055b3d6aaed98aef61d43cbff57fcddd0531008d..5d50c7795dd547674e76e05c9dae9b87b209d8de 100644 (file)
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -451,6 +451,16 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
                        P.replace(pm.sigmap(D), Q);
                        st.ffP->connections_.at("\\Q").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
 
+                       for (auto c : Q.chunks()) {
+                               auto it = c.wire->attributes.find("\\init");
+                               if (it == c.wire->attributes.end())
+                                       continue;
+                               for (int i = c.offset; i < c.offset+c.width; i++) {
+                                       log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
+                                       it->second[i] = State::Sx;
+                               }
+                       }
+
                        cell->setParam("\\PREG", State::S1);
                }
 

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 05837d057cb8692acec398c89c722fd3a1f80908..7db8e95a6bcdc10dcdedb3253132acbc7db347cb 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -290,8 +290,8 @@ endmatch
 
 code argQ
        if (ff) {
-               for (auto b : argQ)
-                       if (b.wire->get_bool_attribute(\keep))
+               for (auto c : argQ.chunks())
+                       if (c.wire->get_bool_attribute(\keep))
                                reject;
 
                if (clock != SigBit()) {
@@ -447,9 +447,13 @@ code
        if (dff) {
                dffQ = port(dff, \Q);
 
-               for (auto b : dffQ)
-                       if (b.wire->get_bool_attribute(\keep))
+               for (auto c : dffQ.chunks()) {
+                       if (c.wire->get_bool_attribute(\keep))
                                reject;
+                       Const init = c.wire->attributes.at(\init, State::Sx);
+                       if (!init.is_fully_undef() && !init.is_fully_zero())
+                               reject;
+               }
 
                if (clock != SigBit()) {
                        if (port(dff, \CLK) != clock)