+2001-01-05 Richard Earnshaw <rearnsha@arm.com>
+
+ * arm.md (ldmsi_postinc): Avoid use of match_dup between input and
+ output operands. Use arm_hard_register_operand for operand 4.
+ (stmsi_postinc): Similarly.
+ (ldmsi): Use arm_hard_register_operand for opernand 2.
+ (stmsi): Similarly.
+ * arm.c (arm_hard_register_operand): New function.
+ * arm-protos.h (arm_hard_register_operand): Prototype it.
+
+ * arm.h (HARD_REGNO_RENAME_OK): Define.
+
Fri Jan 5 16:29:49 MET 2001 Jan Hubicka <jh@suse.cz>
* simplify-rtx.c (cfc_args): add "unordered" field.
/* Prototypes for exported functions defined in arm.c and pe.c
- Copyright (C) 1999, 2000 Free Software Foundation, Inc.
+ Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
Contributed by Richard Earnshaw (rearnsha@arm.com)
Minor hacks by Nick Clifton (nickc@cygnus.com)
/* Predicates. */
extern int s_register_operand PARAMS ((rtx, enum machine_mode));
+extern int arm_hard_register_operand PARAMS ((rtx, enum machine_mode));
extern int f_register_operand PARAMS ((rtx, enum machine_mode));
extern int reg_or_int_operand PARAMS ((rtx, enum machine_mode));
extern int arm_reload_memory_operand PARAMS ((rtx, enum machine_mode));
extern void arm_poke_function_name PARAMS ((FILE *, char *));
extern void output_arm_prologue PARAMS ((FILE *, int));
extern void arm_print_operand PARAMS ((FILE *, rtx, int));
+extern void arm_print_operand_address PARAMS ((FILE *, rtx));
extern void arm_final_prescan_insn PARAMS ((rtx));
extern int arm_go_if_legitimate_address PARAMS ((enum machine_mode, rtx));
extern int arm_debugger_arg_offset PARAMS ((int, rtx));
/* Output routines for GCC for ARM.
- Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
+ Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
Free Software Foundation, Inc.
Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
and Martin Simmons (@harleqn.co.uk).
|| REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
}
+/* A hard register operand (even before reload. */
+int
+arm_hard_register_operand (op, mode)
+ register rtx op;
+ enum machine_mode mode;
+{
+ if (GET_MODE (op) != mode && mode != VOIDmode)
+ return 0;
+
+ return (GET_CODE (op) == REG
+ && REGNO (op) < FIRST_PSEUDO_REGISTER);
+}
+
/* Only accept reg, subreg(reg), const_int. */
int
: \
((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
\f
+/* Register Renaming Parameters. */
+
+/* A C expression that is nonzero if hard register number TO can be
+ considered for use as a rename register for FROM.
+
+ If the return register isn't already live, we mustn't use it. */
+
+#define HARD_REGNO_RENAME_OK(FROM,TO) \
+ ((TO) != LR_REGNUM || regs_ever_live[LR_REGNUM])
+
+\f
/* Stack layout; function entry, exit and calling. */
/* Define this if pushing a word on the stack
;;- Machine description for ARM for GNU compiler
-;; Copyright 1991, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999, 2000
+;; Copyright 1991, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999, 2000, 2001
;; Free Software Foundation, Inc.
;; Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
;; and Martin Simmons (@harleqn.co.uk).
(define_insn "*ldmsi_postinc"
[(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 1 "s_register_operand" "+r")
- (plus:SI (match_dup 1)
- (match_operand:SI 2 "const_int_operand" "n")))
- (set (match_operand:SI 3 "s_register_operand" "=r")
- (mem:SI (match_dup 1)))])]
- "TARGET_ARM && (INTVAL (operands[2]) == 4 * (XVECLEN (operands[0], 0) - 1))"
+ [(set (match_operand:SI 1 "s_register_operand" "=r")
+ (plus:SI (match_operand:SI 2 "s_register_operand" "1")
+ (match_operand:SI 3 "const_int_operand" "n")))
+ (set (match_operand:SI 4 "arm_hard_register_operand" "")
+ (mem:SI (match_dup 2)))])]
+ "TARGET_ARM && (INTVAL (operands[3]) == 4 * (XVECLEN (operands[0], 0) - 1))"
"*
{
rtx ops[3];
(define_insn "*ldmsi"
[(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 1 "s_register_operand" "=r")
+ [(set (match_operand:SI 1 "arm_hard_register_operand" "")
(mem:SI (match_operand:SI 2 "s_register_operand" "r")))])]
"TARGET_ARM"
"*
(define_insn "*stmsi_postinc"
[(match_parallel 0 "store_multiple_operation"
- [(set (match_operand:SI 1 "s_register_operand" "+r")
- (plus:SI (match_dup 1)
- (match_operand:SI 2 "const_int_operand" "n")))
- (set (mem:SI (match_dup 1))
- (match_operand:SI 3 "s_register_operand" "r"))])]
- "TARGET_ARM && (INTVAL (operands[2]) == 4 * (XVECLEN (operands[0], 0) - 1))"
+ [(set (match_operand:SI 1 "s_register_operand" "=r")
+ (plus:SI (match_operand:SI 2 "s_register_operand" "1")
+ (match_operand:SI 3 "const_int_operand" "n")))
+ (set (mem:SI (match_dup 2))
+ (match_operand:SI 4 "arm_hard_register_operand" ""))])]
+ "TARGET_ARM && (INTVAL (operands[3]) == 4 * (XVECLEN (operands[0], 0) - 1))"
"*
{
rtx ops[3];
(define_insn "*stmsi"
[(match_parallel 0 "store_multiple_operation"
- [(set (mem:SI (match_operand:SI 2 "s_register_operand" "r"))
- (match_operand:SI 1 "s_register_operand" "r"))])]
+ [(set (mem:SI (match_operand:SI 1 "s_register_operand" "r"))
+ (match_operand:SI 2 "arm_hard_register_operand" ""))])]
"TARGET_ARM"
"*
{