soc/cores/spi: make cs/loopback CSR optional.

Useful for API retro-compatibility.

diff --git a/litex/soc/cores/spi.py b/litex/soc/cores/spi.py
index fe09f5e9e34b0f5552dc8b09e1aa31a0284125fb..9ed595a1f72576a2706219726467b9e73b24ec0c 100644 (file)
--- a/litex/soc/cores/spi.py
+++ b/litex/soc/cores/spi.py
@@ -127,7 +127,7 @@ class SPIMaster(Module, AutoCSR):
             )
         ]
 
-    def add_csr(self):
+    def add_csr(self, with_cs=True, with_loopback=True):
         self._control  = CSRStorage(fields=[
             CSRField("start",  size=1, offset=0, pulse=True, description="Write ``1`` to start SPI Xfer"),
             CSRField("length", size=8, offset=8, description="SPI Xfer length (in bits).")
@@ -137,21 +137,21 @@ class SPIMaster(Module, AutoCSR):
         ], description="SPI Status.")
         self._mosi     = CSRStorage(self.data_width, reset_less=True, description="SPI MOSI data (MSB-first serialization).")
         self._miso     = CSRStatus(self.data_width,  description="SPI MISO data (MSB-first de-serialization).")
-        self._cs       = CSRStorage(fields=[
-            CSRField("sel", len(self.cs), reset=1, description="Write ``1`` to corresponding bit to enable Xfer for chip.")
-        ], description="SPI Chip Select.")
-        self._loopback = CSRStorage(description="SPI loopback mode.\n\n Write ``1`` to enable MOSI to MISO internal loopback.")
-
         self.comb += [
             self.start.eq(self._control.fields.start),
             self.length.eq(self._control.fields.length),
             self.mosi.eq(self._mosi.storage),
-            self.cs.eq(self._cs.storage),
-            self.loopback.eq(self._loopback.storage),
-
             self._status.fields.done.eq(self.done),
             self._miso.status.eq(self.miso),
         ]
+        if with_cs:
+            self._cs       = CSRStorage(fields=[
+                CSRField("sel", len(self.cs), reset=1, description="Write ``1`` to corresponding bit to enable Xfer for chip.")
+            ], description="SPI Chip Select.")
+            self.comb += self.cs.eq(self._cs.storage)
+        if with_loopback:
+            self._loopback = CSRStorage(description="SPI loopback mode.\n\n Write ``1`` to enable MOSI to MISO internal loopback.")
+            self.comb += self.loopback.eq(self._loopback.storage)
 
     def add_clk_divider(self):
         self._clk_divider = CSRStorage(16, description="SPI Clk Divider.", reset=self.clk_divider.reset)