Added "init" attribute support to verilog backend

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index ba57e88140f3294ea000a7cb608285fe94ed29e9..0d667c638f9aab5efaf782c119215b9b28f0325c 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -299,6 +299,11 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
                f << stringf("%s" "reg%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
        else if (!wire->port_input && !wire->port_output)
                f << stringf("%s" "wire%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
+       if (wire->attributes.count("\\init")) {
+               f << stringf("%s" "initial %s = ", indent.c_str(), id(wire->name).c_str());
+               dump_const(f, wire->attributes.at("\\init"));
+               f << stringf(";\n");
+       }
 #endif
 }