self.bridge.side_a = self.iobus.port
self.bridge.side_b = self.membus.port
- # Serial port and console
- self.console = SimConsole()
- self.com_1 = Uart8250()
- self.com_1.pio_addr = x86IOAddress(0x3f8)
- self.com_1.pio = self.iobus.port
- self.com_1.sim_console = self.console
-
# Command line
self.boot_osflags = 'earlyprintk=ttyS0'
# Platform
- self.opteron = Opteron()
- self.opteron.attachIO(self.iobus)
+ self.pc = PC()
+ self.pc.attachIO(self.iobus)
self.intrctrl = IntrControl()
+++ /dev/null
-from m5.params import *
-from m5.proxy import *
-from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
-from Uart import Uart8250
-from Platform import Platform
-from Pci import PciConfigAll
-from SimConsole import SimConsole
-
-class Opteron(Platform):
- type = 'Opteron'
- system = Param.System(Parent.any, "system")
-
- pciconfig = PciConfigAll()
-
- def attachIO(self, bus):
- self.pciconfig.pio = bus.default
- bus.responder_set = True
- bus.responder = self.pciconfig
--- /dev/null
+# Copyright (c) 2008 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.params import *
+from m5.proxy import *
+from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
+from Uart import Uart8250
+from Platform import Platform
+from Pci import PciConfigAll
+from SimConsole import SimConsole
+
+def x86IOAddress(port):
+ IO_address_space_base = 0x8000000000000000
+ return IO_address_space_base + port;
+
+class PC(Platform):
+ type = 'PC'
+ system = Param.System(Parent.any, "system")
+
+ pciconfig = PciConfigAll()
+
+ # Serial port and console
+ console = SimConsole()
+ com_1 = Uart8250()
+ com_1.pio_addr = x86IOAddress(0x3f8)
+ com_1.sim_console = console
+
+ def attachIO(self, bus):
+ self.com_1.pio = bus.port
+ self.pciconfig.pio = bus.default
+ bus.responder_set = True
+ bus.responder = self.pciconfig
Import('*')
if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
- SimObject('Opteron.py')
+ SimObject('PC.py')
- Source('opteron.cc')
+ Source('pc.cc')
+++ /dev/null
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-/** @file
- * Implementation of Opteron platform.
- */
-
-#include <deque>
-#include <string>
-#include <vector>
-
-#include "arch/x86/x86_traits.hh"
-#include "cpu/intr_control.hh"
-#include "dev/simconsole.hh"
-#include "dev/x86/opteron.hh"
-#include "sim/system.hh"
-
-using namespace std;
-using namespace TheISA;
-
-Opteron::Opteron(const Params *p)
- : Platform(p), system(p->system)
-{
- // set the back pointer from the system to myself
- system->platform = this;
-}
-
-Tick
-Opteron::intrFrequency()
-{
- panic("Need implementation\n");
- M5_DUMMY_RETURN
-}
-
-void
-Opteron::postConsoleInt()
-{
- warn_once("Don't know what interrupt to post for console.\n");
- //panic("Need implementation\n");
-}
-
-void
-Opteron::clearConsoleInt()
-{
- warn_once("Don't know what interrupt to clear for console.\n");
- //panic("Need implementation\n");
-}
-
-void
-Opteron::postPciInt(int line)
-{
- panic("Need implementation\n");
-}
-
-void
-Opteron::clearPciInt(int line)
-{
- panic("Need implementation\n");
-}
-
-Addr
-Opteron::pciToDma(Addr pciAddr) const
-{
- panic("Need implementation\n");
- M5_DUMMY_RETURN
-}
-
-
-Addr
-Opteron::calcConfigAddr(int bus, int dev, int func)
-{
- assert(func < 8);
- assert(dev < 32);
- assert(bus == 0);
- return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
-}
-
-Opteron *
-OpteronParams::create()
-{
- return new Opteron(this);
-}
+++ /dev/null
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-/**
- * @file
- * Declaration of top level class for the Opteron platform chips. This class
- * just retains pointers to all its children so the children can communicate.
- */
-
-#ifndef __DEV_Opteron_HH__
-#define __DEV_Opteron_HH__
-
-#include "dev/platform.hh"
-#include "params/Opteron.hh"
-
-class IdeController;
-class System;
-
-class Opteron : public Platform
-{
- public:
- /** Pointer to the system */
- System *system;
-
- public:
- typedef OpteronParams Params;
-
- Opteron(const Params *p);
-
- /**
- * Return the interrupting frequency to AlphaAccess
- * @return frequency of RTC interrupts
- */
- virtual Tick intrFrequency();
-
- /**
- * Cause the cpu to post a serial interrupt to the CPU.
- */
- virtual void postConsoleInt();
-
- /**
- * Clear a posted CPU interrupt
- */
- virtual void clearConsoleInt();
-
- /**
- * Cause the chipset to post a pci interrupt to the CPU.
- */
- virtual void postPciInt(int line);
-
- /**
- * Clear a posted PCI->CPU interrupt
- */
- virtual void clearPciInt(int line);
-
-
- virtual Addr pciToDma(Addr pciAddr) const;
-
- /**
- * Calculate the configuration address given a bus/dev/func.
- */
- virtual Addr calcConfigAddr(int bus, int dev, int func);
-};
-
-#endif // __DEV_OPTERON_HH__
--- /dev/null
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+/** @file
+ * Implementation of PC platform.
+ */
+
+#include <deque>
+#include <string>
+#include <vector>
+
+#include "arch/x86/x86_traits.hh"
+#include "cpu/intr_control.hh"
+#include "dev/simconsole.hh"
+#include "dev/x86/pc.hh"
+#include "sim/system.hh"
+
+using namespace std;
+using namespace TheISA;
+
+PC::PC(const Params *p)
+ : Platform(p), system(p->system)
+{
+ // set the back pointer from the system to myself
+ system->platform = this;
+}
+
+Tick
+PC::intrFrequency()
+{
+ panic("Need implementation\n");
+ M5_DUMMY_RETURN
+}
+
+void
+PC::postConsoleInt()
+{
+ warn_once("Don't know what interrupt to post for console.\n");
+ //panic("Need implementation\n");
+}
+
+void
+PC::clearConsoleInt()
+{
+ warn_once("Don't know what interrupt to clear for console.\n");
+ //panic("Need implementation\n");
+}
+
+void
+PC::postPciInt(int line)
+{
+ panic("Need implementation\n");
+}
+
+void
+PC::clearPciInt(int line)
+{
+ panic("Need implementation\n");
+}
+
+Addr
+PC::pciToDma(Addr pciAddr) const
+{
+ panic("Need implementation\n");
+ M5_DUMMY_RETURN
+}
+
+
+Addr
+PC::calcConfigAddr(int bus, int dev, int func)
+{
+ assert(func < 8);
+ assert(dev < 32);
+ assert(bus == 0);
+ return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
+}
+
+PC *
+PCParams::create()
+{
+ return new PC(this);
+}
--- /dev/null
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+/**
+ * @file
+ * Declaration of top level class for PC platform components. This class
+ * just retains pointers to all its children so the children can communicate.
+ */
+
+#ifndef __DEV_PC_HH__
+#define __DEV_PC_HH__
+
+#include "dev/platform.hh"
+#include "params/PC.hh"
+
+class IdeController;
+class System;
+
+class PC : public Platform
+{
+ public:
+ /** Pointer to the system */
+ System *system;
+
+ public:
+ typedef PCParams Params;
+
+ PC(const Params *p);
+
+ /**
+ * Return the interrupting frequency to AlphaAccess
+ * @return frequency of RTC interrupts
+ */
+ virtual Tick intrFrequency();
+
+ /**
+ * Cause the cpu to post a serial interrupt to the CPU.
+ */
+ virtual void postConsoleInt();
+
+ /**
+ * Clear a posted CPU interrupt
+ */
+ virtual void clearConsoleInt();
+
+ /**
+ * Cause the chipset to post a pci interrupt to the CPU.
+ */
+ virtual void postPciInt(int line);
+
+ /**
+ * Clear a posted PCI->CPU interrupt
+ */
+ virtual void clearPciInt(int line);
+
+
+ virtual Addr pciToDma(Addr pciAddr) const;
+
+ /**
+ * Calculate the configuration address given a bus/dev/func.
+ */
+ virtual Addr calcConfigAddr(int bus, int dev, int func);
+};
+
+#endif // __DEV_PC_HH__
projects / gem5.git / commitdiff