sort out image scaling

diff --git a/openpower/pandoc_img.py b/openpower/pandoc_img.py
index cdbce788a061edbc55cf1e929f2c0878262fd8bb..e9f0b376a654356a37b7134c3a7062effa73acc9 100755 (executable)
--- a/openpower/pandoc_img.py
+++ b/openpower/pandoc_img.py
@@ -91,6 +91,7 @@ def inlinenotes(k, v, f, meta):
                    'isa/svfparith' : 'Floating Point pseudocode',
                    'isa/svfixedarith' : 'Fixed Point pseudocode',
                    'openpower/isa/branch' : 'Branch pseudocode',
+                   'openpower/transcendentals' : 'Transcendentals',
                   }
         if link in lookups:
             out.write("     found %s\n" % lookups[link])

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 91385e752f604d55b8e246186ef862c65874586b..758a64260da05968944f741c23be38ef0118b005 100644 (file)
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -77,7 +77,7 @@ a register file size
 increase using "tagging" (similar to how x86 originally extended
 registers from 32 to 64 bit).
 
-![Single-Issue concept](/openpower/svp64-primer/img/power_pipelines.svg)
+![Single-Issue concept](/openpower/svp64-primer/img/power_pipelines.svg){ width=40% height=20% }
 
 ## SV
 
@@ -95,7 +95,7 @@ The fundamentals are (just like x86 "REP"):
 * Once the loop is completed *only then* is the Program Counter
   allowed to move to the next instruction.
 
-![Multi-Issue with Predicated SIMD back-end ALUs](/openpower/svp64-primer/img/sv_multi_issue.svg)
+![Multi-Issue with Predicated SIMD back-end ALUs](/openpower/svp64-primer/img/sv_multi_issue.svg){ width=40% height=40% }
 
 Hardware (and simulator) implementors are free and clear to implement this
 as literally a for-loop, sitting in between instruction decode and issue.
@@ -383,7 +383,7 @@ This means that Vector elements start from locations specified by 64 bit
 "register" but that from that location onwards the elements *overlap
 subsequent registers*.
 
-![image](/openpower/svp64-primer/img/svp64_regs.svg){ width=40% }
+![image](/openpower/svp64-primer/img/svp64_regs.svg){ width=40% height=40% }
 
 Here is another way to view the same concept, bearing in mind that it
 is assumed a LE memory order:
@@ -921,6 +921,8 @@ entirely paralleliseable.
 
 # Vertical-First Mode
 
+![image](/openpower/sv/sv_horizontal_vs_vertical.svg){ width=40% height=40% }
+
 This is a relatively new addition to SVP64 under development as of
 July 2021.  Where Horizontal-First is the standard Cray-style for-loop,
 Vertical-First typically executes just the **one** scalar element
@@ -939,8 +941,6 @@ loop:
   beq loop
 ```
 
-![image](/openpower/sv/sv_horizontal_vs_vertical.svg)
-
 Three examples are illustrated of different types of Scalar-Vector
 operations. Note that in its simplest form  **only one** element is
 executed per instruction **not** multiple elements per instruction.