fix svindex pseudocode

rename RS to SVG in SVI-Form (svindex) to avoid a register name conflict
start checking things properly in test_caller_svindex.py

diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn
index 707cbc5b8fefa80795efdad5cb2282240249491e..fd3ed3b570c3549cd4ddf281a25b162fa5da5081 100644 (file)
--- a/openpower/isa/simplev.mdwn
+++ b/openpower/isa/simplev.mdwn
@@ -269,25 +269,24 @@ Special Registers Altered:
 
 SVI-Form
 
-* svindex RS,rmm,SVd,ew,yx,mr,sk
+* svindex SVG,rmm,SVd,ew,yx,mr,sk
 
 Pseudo-code:
 
     # VL in Matrix Multiply is xd*yd*zd
-    n <- (0b00 || SVxd) * (0b00 || SVyd) * (0b00 || SVzd)
     # set up template, then copy once location identified
-    shape = [0]*32
+    shape <- [0]*32
     shape[30:31] <- 0b00            # mode
     if yx = 0 then
-        shape[18:20] = 0b110        # indexed xd/yd
+        shape[18:20] <- 0b110       # indexed xd/yd
         shape[0:5] <- 0             # xdim
         shape[6:11] <- (0b0 || SVd) # ydim
     else
-        shape[18:20] = 0b111        # indexed yd/xd
+        shape[18:20] <- 0b111       # indexed yd/xd
         shape[0:5] <- (0b0 || SVd)  # xdim
         shape[6:11] <- 0            # ydim
-    shape[12:17] <- (0b0 || SVzd || 0b0)   # SVGPR
-    shape[28:29] <- ew                     # element-width override
+    shape[12:17] <- (0b0 || SVG)        # SVGPR
+    shape[28:29] <- ew                  # element-width override
     if sk = 1 then shape[28:29] <- 0b01 # skip 1st dimension
     else           shape[28:29] <- 0b00 # no skipping
     # select the mode for updating SVSHAPEs
@@ -302,7 +301,7 @@ Pseudo-code:
         SVSTATE[42:46] <- rmm # rmm exactly REMAP.SVme
         idx <- 0
         for bit = 0 to 4
-            if rmm[bit] then
+            if rmm[4-bit] then
                 # activate requested shape
                 if idx = 0 then SVSHAPE0 <- shape
                 if idx = 1 then SVSHAPE1 <- shape

diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text
index ef28fa8d4f531917de3b5848ff6cd21a8a433bc4..25759a90f37c058f2b53736b92dfaa083e84356f 100644 (file)
--- a/openpower/isatables/fields.text
+++ b/openpower/isatables/fields.text
@@ -274,7 +274,7 @@
 
 # 1.6.29 SVI-FORM
     |0     |6    |11    |16   |21 |23|24|25|26    31|
-    | PO   |  RS |rmm   | SVd |ew |yx|mm|sk|   XO   |
+    | PO   |  SVG|rmm   | SVd |ew |yx|mm|sk|   XO   |
 
 # 1.6.30 SVL-FORM
     |0     |6    |11    |16   |23 |24 |25 |26    |31 |
@@ -749,7 +749,7 @@
     RS (6:10)
         Field used to specify a GPR to be used as a
         source.
-        Formats: D, DS, M, MD, MDS, SVI, X, XFX, XS
+        Formats: D, DS, M, MD, MDS, X, XFX, XS
     RSp (6:10)
         Field used to specify an even/odd pair of GPRs to
         be concatenated and used as a source.
@@ -842,6 +842,10 @@
         two's complement integer which is concatenated
         on the right with 0b00 and sign-extended to 64 bits.
         Formats: SVDS
+    SVG (6:10)
+        Field used to specify a GPR to be used as a
+        source for indexing.
+        Formats: SVI
     SVi (16:22)
          Simple-V immediate field for setting VL or MVL
          Formats: SVL

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 7f57d29397e47e1cae713da2497e4197346afee3..859f521122bfe806d6da2c8e7229d36a5130d088 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1248,6 +1248,11 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
             illegal = False
             ins_name = 'svshape'
 
+        # and svindex
+        if asmop.startswith('svindex'):
+            illegal = False
+            ins_name = "svindex"
+
         # and fsin and fcos
         if asmop == 'fsins':
             illegal = False

diff --git a/src/openpower/decoder/isa/test_caller_svindex.py b/src/openpower/decoder/isa/test_caller_svindex.py
index 39ea23edf327ec7dc24943e8aa2085e972d9bcbb..d0d23b3a4f067d834155ecae2b5dd0746127e2f3 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svindex.py
+++ b/src/openpower/decoder/isa/test_caller_svindex.py
@@ -1,4 +1,5 @@
-"""SVP64 unit test for doing strange things to SVSTATE, manually.
+"""SVP64 unit test for svindex
+svindex SVG,rmm,SVd,ew,yx,mr,sk
 """
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay, Settle
@@ -27,15 +28,9 @@ class SVSTATETestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
 
     def test_sv_index(self):
-        """sets VL=2 (via SVSTATE) with a manual srcstep/dststep,
-            then does a scalar-result add.  the result should be:
-
-                add 1, 6, 10
-
-            because whilst the Vector instruction was moved on by srcstep,
-            the Scalar one is NOT moved on.
+        """sets VL=10 (via SVSTATE) then does svindex, checks SPRs after
         """
-        isa = SVP64Asm(['svindex 1, 31, 5, 0, 0, 0, 0'
+        isa = SVP64Asm(['svindex 1, 15, 5, 0, 0, 0, 0'
                        ])
         lst = list(isa)
         print ("listing", lst)
@@ -61,6 +56,8 @@ class SVSTATETestCase(FHDLTestCase):
             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
             self._check_regs(sim, expected_regs)
 
+            print (sim.spr)
+            SVSHAPE0 = sim.spr['SVSHAPE0']
             print ("SVSTATE after", bin(sim.svstate.asint()))
             print ("        vl", bin(sim.svstate.vl))
             print ("        mvl", bin(sim.svstate.maxvl))
@@ -73,6 +70,18 @@ class SVSTATETestCase(FHDLTestCase):
             print ("        mi0", bin(sim.svstate.mi0))
             print ("        mi1", bin(sim.svstate.mi1))
             print ("        mi2", bin(sim.svstate.mi2))
+            print ("STATE0svgpr", hex(SVSHAPE0.svgpr))
+            self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0
+            self.assertEqual(sim.svstate.SVme, 0b01111) # same as rmm
+            # rmm is 0b01111 which means mi0=0 mi1=1 mi2=2 mo0=3 mo1=0
+            self.assertEqual(sim.svstate.mi0, 0)
+            self.assertEqual(sim.svstate.mi1, 1)
+            self.assertEqual(sim.svstate.mi2, 2)
+            self.assertEqual(sim.svstate.mo0, 3)
+            self.assertEqual(sim.svstate.mo1, 0)
+            for i in range(4):
+                shape = sim.spr['SVSHAPE%d' % i]
+                self.assertEqual(shape.svgpr, 2) # SVG is shifted up by 1
 
     def run_tst_program(self, prog, initial_regs=None,
                               svstate=None):