This increases the number of L2 lines from 32 to 64. The BRAM usage is the
same as they were only half used. There's an increase in LUTs and registers
due to the extra tags and valid bits, but none of it should be in a
space constrained or critical timing path.
We could make it wider instead (256 bytes lines) which would reduce usage
instead, but this increases the latency by 8 cycles. Something to consider
once the L2 is capable of early response on miss and starting reloads
from any point in a line.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-- Line size in bytes
LINE_SIZE : positive := 128;
-- Number of lines in a set
- NUM_LINES : positive := 32;
+ NUM_LINES : positive := 64;
-- Number of ways
NUM_WAYS : positive := 4;
-- Max number of stores in the queue