+2008-01-04 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-ppc.c (parse_cpu): Preserve the settings of the
+ PPC_OPCODE_ALTIVEC and PPC_OPCODE_SPE flags.
+
2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (md_assemble): Use !intel_mnemonic instead
static int
parse_cpu (const char *arg)
{
+ unsigned long altivec_or_spe = ppc_cpu & (PPC_OPCODE_ALTIVEC | PPC_OPCODE_SPE);
+
/* -mpwrx and -mpwr2 mean to assemble for the IBM POWER/2
(RIOS2). */
if (strcmp (arg, "pwrx") == 0 || strcmp (arg, "pwr2") == 0)
else if (strcmp (arg, "altivec") == 0)
{
if (ppc_cpu == 0)
- ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ALTIVEC;
- else
- ppc_cpu |= PPC_OPCODE_ALTIVEC;
+ ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC;
+
+ altivec_or_spe |= PPC_OPCODE_ALTIVEC;
}
else if (strcmp (arg, "e500") == 0 || strcmp (arg, "e500x2") == 0)
{
else if (strcmp (arg, "spe") == 0)
{
if (ppc_cpu == 0)
- ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_SPE | PPC_OPCODE_EFS;
- else
- ppc_cpu |= PPC_OPCODE_SPE;
+ ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_EFS;
+
+ altivec_or_spe |= PPC_OPCODE_SPE;
}
/* -mppc64 and -m620 mean to assemble for the 64-bit PowerPC
620. */
else
return 0;
+ /* Make sure the the Altivec and SPE bits are not lost. */
+ ppc_cpu |= altivec_or_spe;
return 1;
}
+2008-01-04 Nick Clifton <nickc@redhat.com>
+
+ * gas/ppc/altivec_and_spe.s: New test - checks that ISA extension
+ command line options (-maltivec, -mspe) can be specified before
+ CPU selection command line options.
+ * gas/ppc/altivec_and_spe.d: Expected disassembly.
+ * gas/ppc/ppc.exp: Run the new test
+
2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-9.d: New file.
--- /dev/null
+#as: -maltivec -mspe -mppc64
+#objdump: -d -Mppc64
+#name: Check that ISA extensions can be specified before CPU selection
+
+.*: +file format elf.*-powerpc.*
+
+Disassembly of section \.text:
+
+0+00 <.*>:
+ 0: 7e 00 06 6c dssall
+ 4: 7d 00 83 a6 mtspr 512,r8
+ 8: 4c 00 00 24 rfid