(no commit message)

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index e20d410aced66f4d6cdcf16bdb1aa18b1d17abb5..7d1185c96694e9d6291ee60c64c726cc55a3c370 100644 (file)
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -101,15 +101,16 @@ storing if
 saturation occurred. Integer Operations that produce a Carry-Out (CA, CA32):
 these two bits will be `UNDEFINED` if saturation is also requested.
 
-Post-analysis of the Vector of CRs to find out if any given element hit
-saturation may be done using a mapreduced CR op (cror), or by using the
-new crweird instruction, transferring the relevant CR bits to a scalar
-integer and testing it for nonzero.  see [[sv/cr_int_predication]]
-
 Note that the operation takes place at the maximum bitwidth (max of
 src and dest elwidth) and that truncation occurs to the range of the
 dest elwidth.
 
+*Programmer's Note: Post-analysis of the Vector of CRs to find out if any given element hit
+saturation may be done using a mapreduced CR op (cror), or by using the
+new crweird instruction with Rc=1, which will transfer the required
+CR bits to a scalar integer and update CR0, which will allow testing
+the scalar integer for nonzero.  see [[sv/cr_int_predication]]*
+
 # Reduce mode
 
 Reduction in SVP64 is similar in essence to other Vector Processing