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diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
index 08a6ab83336603d3e28accde7c682fecff902b64..edb6802fd51df742ccf48920e35fb8d293f924f4 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn
+++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
@@ -35,6 +35,18 @@ something like:
 * vspec - 3 bit src / dest scalar-vector extension
 * sat: 0bSU - S=1 signed U=1 unsigned 0b11 reserved
 
+## twin predication, CR based.
+
+separate src and dest predicates are a critical part of SV for provision of VGATHER, VSCATTER, VREDUCE, VSPLAT and many more operations.
+
+Twin CR predication could be done in two ways:
+
+* start from different CRs for the src and dest
+* start from the same CR.
+
+With different bits being selectable (CR[0..3]) starting from the same CR makes some sense.
+
+
 # standard arith ops (single predication)
 
 these are of the form res = op(src1, src2, ...)