i965/state: Clean up WM/PS state to pull more things out of prog_data

Now that we have a persample_shading bit in prog_data we can reduce the
amount the state setup code needs to be looking at the GL state.  In
particular, it no longer pulls anything directly out of the
gl_fragment_program and no longer depends on NEW_FRAGMENT_PROGRAM.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 5c971d13865566543f0a6b1e0aac456f7b56c049..6efcef14e4d31621059c7599216c80de2b337013 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -305,15 +305,12 @@ void gen7_init_vtable_surface_functions(struct brw_context *brw);
 
 /* gen8_ps_state.c */
 void gen8_upload_ps_state(struct brw_context *brw,
-                          const struct gl_fragment_program *fp,
                           const struct brw_stage_state *stage_state,
                           const struct brw_wm_prog_data *prog_data,
                           uint32_t fast_clear_op);
 
 void gen8_upload_ps_extra(struct brw_context *brw,
-                          const struct gl_fragment_program *fp,
-                          const struct brw_wm_prog_data *prog_data,
-                          bool multisampled_fbo);
+                          const struct brw_wm_prog_data *prog_data);
 
 /* gen7_sol_state.c */
 void gen7_upload_3dstate_so_decl_list(struct brw_context *brw,
@@ -370,10 +367,9 @@ void brw_update_sampler_state(struct brw_context *brw,
 /* gen6_wm_state.c */
 void
 gen6_upload_wm_state(struct brw_context *brw,
-                     const struct brw_fragment_program *fp,
                      const struct brw_wm_prog_data *prog_data,
                      const struct brw_stage_state *stage_state,
-                     bool multisampled_fbo, int min_inv_per_frag,
+                     bool multisampled_fbo,
                      bool dual_source_blend_enable, bool kill_enable,
                      bool color_buffer_write_enable, bool msaa_enabled,
                      bool line_stipple_enable, bool polygon_stipple_enable,

diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index dd33926dc82de08bc12e36c473fe5cc24221815c..4a5aa129d41f6bfec6163440ec34d7d98a581fc4 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -69,10 +69,9 @@ const struct brw_tracked_state gen6_wm_push_constants = {
 
 void
 gen6_upload_wm_state(struct brw_context *brw,
-                     const struct brw_fragment_program *fp,
                      const struct brw_wm_prog_data *prog_data,
                      const struct brw_stage_state *stage_state,
-                     bool multisampled_fbo, int min_inv_per_frag,
+                     bool multisampled_fbo,
                      bool dual_source_blend_enable, bool kill_enable,
                      bool color_buffer_write_enable, bool msaa_enabled,
                      bool line_stipple_enable, bool polygon_stipple_enable,
@@ -163,10 +162,11 @@ gen6_upload_wm_state(struct brw_context *brw,
    if (polygon_stipple_enable)
       dw5 |= GEN6_WM_POLYGON_STIPPLE_ENABLE;
 
-   /* BRW_NEW_FRAGMENT_PROGRAM */
-   if (fp->program.Base.InputsRead & VARYING_BIT_POS)
-      dw5 |= GEN6_WM_USES_SOURCE_DEPTH | GEN6_WM_USES_SOURCE_W;
-   if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
+   if (prog_data->uses_src_depth)
+      dw5 |= GEN6_WM_USES_SOURCE_DEPTH;
+   if (prog_data->uses_src_w)
+      dw5 |= GEN6_WM_USES_SOURCE_W;
+   if (prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF)
       dw5 |= GEN6_WM_COMPUTED_DEPTH;
    dw6 |= prog_data->barycentric_interp_modes <<
       GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
@@ -277,23 +277,12 @@ static void
 upload_wm_state(struct brw_context *brw)
 {
    struct gl_context *ctx = &brw->ctx;
-   /* BRW_NEW_FRAGMENT_PROGRAM */
-   const struct brw_fragment_program *fp =
-      brw_fragment_program_const(brw->fragment_program);
    /* BRW_NEW_FS_PROG_DATA */
    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
 
    /* _NEW_BUFFERS */
    const bool multisampled_fbo = _mesa_geometric_samples(ctx->DrawBuffer) > 1;
 
-   /* In case of non 1x per sample shading, only one of SIMD8 and SIMD16
-    * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
-    * is successfully compiled. In majority of the cases that bring us
-    * better performance than 'SIMD8 only' dispatch.
-    */
-   const int min_inv_per_frag = _mesa_get_min_invocations_per_fragment(
-                                   ctx, brw->fragment_program, false);
-
    /* BRW_NEW_FS_PROG_DATA | _NEW_COLOR */
    const bool dual_src_blend_enable = prog_data->dual_src_blend &&
                                       (ctx->Color.BlendEnabled & 1) &&
@@ -310,8 +299,8 @@ upload_wm_state(struct brw_context *brw)
    /* _NEW_LINE | _NEW_POLYGON | _NEW_BUFFERS | _NEW_COLOR |
     * _NEW_MULTISAMPLE
     */
-   gen6_upload_wm_state(brw, fp, prog_data, &brw->wm.base,
-                        multisampled_fbo, min_inv_per_frag,
+   gen6_upload_wm_state(brw, prog_data, &brw->wm.base,
+                        multisampled_fbo,
                         dual_src_blend_enable, kill_enable,
                         brw_color_buffer_write_enabled(brw),
                         ctx->Multisample.Enabled,
@@ -329,7 +318,6 @@ const struct brw_tracked_state gen6_wm_state = {
                _NEW_PROGRAM_CONSTANTS,
       .brw   = BRW_NEW_BATCH |
                BRW_NEW_BLORP |
-               BRW_NEW_FRAGMENT_PROGRAM |
                BRW_NEW_FS_PROG_DATA |
                BRW_NEW_PUSH_CONSTANT_ALLOCATION,
    },

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 945fbbdaa2bb463df24e6ec6672c9c0d48a37037..17dea99a03d513cea7e5b08ef6821abb4afc09a7 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -146,7 +146,6 @@ const struct brw_tracked_state gen7_wm_state = {
 
 static void
 gen7_upload_ps_state(struct brw_context *brw,
-                     const struct gl_fragment_program *fp,
                      const struct brw_stage_state *stage_state,
                      const struct brw_wm_prog_data *prog_data,
                      bool enable_dual_src_blend, unsigned sample_mask,
@@ -278,7 +277,7 @@ upload_ps_state(struct brw_context *brw)
    const unsigned sample_mask =
       brw->is_haswell ? gen6_determine_sample_mask(brw) : 0;
 
-   gen7_upload_ps_state(brw, brw->fragment_program, &brw->wm.base, prog_data,
+   gen7_upload_ps_state(brw, &brw->wm.base, prog_data,
                         enable_dual_src_blend, sample_mask,
                         brw->wm.fast_clear_op);
 }
@@ -290,7 +289,6 @@ const struct brw_tracked_state gen7_ps_state = {
                _NEW_MULTISAMPLE,
       .brw   = BRW_NEW_BATCH |
                BRW_NEW_BLORP |
-               BRW_NEW_FRAGMENT_PROGRAM |
                BRW_NEW_FS_PROG_DATA,
    },
    .emit = upload_ps_state,

diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c
index d3e1ca38c751206ad302479b52283bf4bbf42b2b..b677a8e1793dbcfcd1e4eaa0d33f077d8c12d326 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
@@ -30,9 +30,7 @@
 
 void
 gen8_upload_ps_extra(struct brw_context *brw,
-                     const struct gl_fragment_program *fp,
-                     const struct brw_wm_prog_data *prog_data,
-                     bool multisampled_fbo)
+                     const struct brw_wm_prog_data *prog_data)
 {
    struct gl_context *ctx = &brw->ctx;
    uint32_t dw1 = 0;
@@ -115,15 +113,10 @@ gen8_upload_ps_extra(struct brw_context *brw,
 static void
 upload_ps_extra(struct brw_context *brw)
 {
-   /* BRW_NEW_FRAGMENT_PROGRAM */
-   const struct brw_fragment_program *fp =
-      brw_fragment_program_const(brw->fragment_program);
    /* BRW_NEW_FS_PROG_DATA */
    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
-   /* BRW_NEW_NUM_SAMPLES */
-   const bool multisampled_fbo = brw->num_samples > 1;
 
-   gen8_upload_ps_extra(brw, &fp->program, prog_data, multisampled_fbo);
+   gen8_upload_ps_extra(brw, prog_data);
 }
 
 const struct brw_tracked_state gen8_ps_extra = {
@@ -131,9 +124,7 @@ const struct brw_tracked_state gen8_ps_extra = {
       .mesa  = _NEW_BUFFERS | _NEW_COLOR,
       .brw   = BRW_NEW_BLORP |
                BRW_NEW_CONTEXT |
-               BRW_NEW_FRAGMENT_PROGRAM |
-               BRW_NEW_FS_PROG_DATA |
-               BRW_NEW_NUM_SAMPLES,
+               BRW_NEW_FS_PROG_DATA,
    },
    .emit = upload_ps_extra,
 };
@@ -186,7 +177,6 @@ const struct brw_tracked_state gen8_wm_state = {
 
 void
 gen8_upload_ps_state(struct brw_context *brw,
-                     const struct gl_fragment_program *fp,
                      const struct brw_stage_state *stage_state,
                      const struct brw_wm_prog_data *prog_data,
                      uint32_t fast_clear_op)
@@ -300,8 +290,7 @@ upload_ps_state(struct brw_context *brw)
 {
    /* BRW_NEW_FS_PROG_DATA */
    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
-   gen8_upload_ps_state(brw, brw->fragment_program, &brw->wm.base, prog_data,
-                        brw->wm.fast_clear_op);
+   gen8_upload_ps_state(brw, &brw->wm.base, prog_data, brw->wm.fast_clear_op);
 }
 
 const struct brw_tracked_state gen8_ps_state = {