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invert RC and RA, making divmod2du more like divdu
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 29 Apr 2022 09:33:43 +0000 (10:33 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 29 Apr 2022 09:33:43 +0000 (10:33 +0100)
not divdeu

openpower/isa/svfixedarith.mdwn patch | blob | history

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index ebef59cea55e4934c1d4c3becb5e14019d51ea25..cf8834502445c0aa20646abe2144edc35c917b19 100644 (file)
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -18,7 +18,7 @@ Special Registers Altered:
 
     None
 
-# [DRAFT] Twin Divide Quad Unsigned
+# [DRAFT] Twin Divide/Modulo Quad Unsigned
 
 VA-Form
 
@@ -30,7 +30,7 @@ Pseudo-code:
     <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL -->
     <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]    -->
     if ((RA) <u (RB)) & ((RB) != [0]*XLEN) then
-        dividend[0:(XLEN*2)-1] <- (RA) || (RC)
+        dividend[0:(XLEN*2)-1] <- (RC) || (RA)
         divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
         result <- dividend / divisor
         modulo <- dividend % divisor