integration/soc: add expection on decoder when full address space is mapped.

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 4a459ed1058ce0ce0811ed679690fc61a2d2a9a3..feff41c75b7aa480be6a0012ec2fbe38f464dbb0 100644 (file)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -73,6 +73,8 @@ class SoCRegion:
             self.logger.error("Origin needs to be aligned on size:")
             self.logger.error(self)
             raise
+        if (origin == 0) and (size == 2**bus.address_width):
+            return lambda a : True
         origin >>= int(log2(bus.data_width//8)) # bytes to words aligned
         size   >>= int(log2(bus.data_width//8)) # bytes to words aligned
         return lambda a: (a[log2_int(size):] == (origin >> log2_int(size)))
@@ -843,6 +845,7 @@ class SoC(Module):
                     name             = "SoCDMABusHandler",
                     standard         = "wishbone",
                     data_width       = self.bus.data_width,
+                    address_width    = self.bus.address_width,
                 )
                 dma_bus = wishbone.Interface(data_width=self.bus.data_width)
                 self.dma_bus.add_slave("dma", slave=dma_bus, region=SoCRegion(origin=0x00000000, size=0x100000000)) # FIXME: covers lower 4GB only