return true;
}
+template <class XC>
+inline void
+globalClearExclusive(XC *xc)
+{
+ xc->getCpuPtr()->wakeup(xc->threadId());
+}
+
} // namespace AlphaISA
#endif // __ARCH_ALPHA_LOCKED_MEM_HH__
/*
- * Copyright (c) 2012-2013 ARM Limited
+ * Copyright (c) 2012-2013,2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
return true;
}
+template <class XC>
+inline void
+globalClearExclusive(XC *xc)
+{
+ // A spinlock would typically include a Wait For Event (WFE) to
+ // conserve energy. The ARMv8 architecture specifies that an event
+ // is automatically generated when clearing the exclusive monitor
+ // to wake up the processor in WFE.
+ DPRINTF(LLSC,"Clearing lock and signaling sev\n");
+ xc->setMiscReg(MISCREG_LOCKFLAG, false);
+ // Implement ARMv8 WFE/SEV semantics
+ xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
+ xc->getCpuPtr()->wakeup(xc->threadId());
+}
} // namespace ArmISA
--- /dev/null
+/*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ */
+
+#ifndef __ARCH_GENERIC_LOCKED_MEM_HH__
+#define __ARCH_GENERIC_LOCKED_MEM_HH__
+
+/**
+ * @file
+ *
+ * Generic helper functions for locked memory accesses.
+ */
+
+#include "config/the_isa.hh"
+#include "mem/packet.hh"
+#include "mem/request.hh"
+
+namespace TheISA
+{
+template <class XC>
+inline void
+handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
+{
+}
+
+template <class XC>
+inline void
+handleLockedRead(XC *xc, Request *req)
+{
+}
+
+template <class XC>
+inline void
+handleLockedSnoopHit(XC *xc)
+{
+}
+
+
+template <class XC>
+inline bool
+handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
+{
+ return true;
+}
+
+template <class XC>
+inline void
+globalClearExclusive(XC *xc)
+{
+}
+
+} // namespace Generic ISA
+
+#endif
return true;
}
+template <class XC>
+inline void
+globalClearExclusive(XC *xc)
+{
+ xc->getCpuPtr()->wakeup(xc->threadId());
+}
+
} // namespace MipsISA
#endif
--- /dev/null
+/*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ */
+
+#ifndef __ARCH_NULL_LOCKED_MEM_HH__
+#define __ARCH_NULL_LOCKED_MEM_HH__
+
+/**
+ * @file
+ *
+ * ISA-specific helper functions for locked memory accesses.
+ */
+
+#include "arch/generic/locked_mem.hh"
+
+#endif
* ISA-specific helper functions for locked memory accesses.
*/
-#include "mem/packet.hh"
-#include "mem/request.hh"
-
-namespace PowerISA
-{
-
-template <class XC>
-inline void
-handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
-{
-}
-
-template <class XC>
-inline void
-handleLockedRead(XC *xc, Request *req)
-{
-}
-
-template <class XC>
-inline void
-handleLockedSnoopHit(XC *xc)
-{
-}
-
-template <class XC>
-inline bool
-handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
-{
- return true;
-}
-
-} // namespace PowerISA
+#include "arch/generic/locked_mem.hh"
#endif // __ARCH_POWER_LOCKED_MEM_HH__
return true;
}
+template <class XC>
+inline void
+globalClearExclusive(XC *xc)
+{
+ xc->getCpuPtr()->wakeup(xc->threadId());
+}
+
} // namespace RiscvISA
#endif // __ARCH_RISCV_LOCKED_MEM_HH__
* ISA-specific helper functions for locked memory accesses.
*/
-#include "mem/packet.hh"
-#include "mem/request.hh"
-
-namespace SparcISA
-{
-template <class XC>
-inline void
-handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
-{
-}
-
-template <class XC>
-inline void
-handleLockedRead(XC *xc, Request *req)
-{
-}
-
-template <class XC>
-inline void
-handleLockedSnoopHit(XC *xc)
-{
-}
-
-
-template <class XC>
-inline bool
-handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
-{
- return true;
-}
-
-
-} // namespace SparcISA
+#include "arch/generic/locked_mem.hh"
#endif
* ISA-specific helper functions for locked memory accesses.
*/
-#include "mem/packet.hh"
-#include "mem/request.hh"
-
-namespace X86ISA
-{
- template <class XC>
- inline void
- handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
- {
- }
-
- template <class XC>
- inline void
- handleLockedRead(XC *xc, Request *req)
- {
- }
-
- template <class XC>
- inline bool
- handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
- {
- return true;
- }
-
- template <class XC>
- inline void
- handleLockedSnoopHit(XC *xc)
- {
- }
-}
+#include "arch/generic/locked_mem.hh"
#endif // __ARCH_X86_LOCKEDMEM_HH__
/*
- * Copyright (c) 2010-2012 ARM Limited
+ * Copyright (c) 2010-2012,2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
#include <vector>
+#include "arch/locked_mem.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/LLSC.hh"
if (i->addr == paddr) {
DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n",
i->contextId, paddr);
- // For ARM, a spinlock would typically include a Wait
- // For Event (WFE) to conserve energy. The ARMv8
- // architecture specifies that an event is
- // automatically generated when clearing the exclusive
- // monitor to wake up the processor in WFE.
- ThreadContext* ctx = system()->getThreadContext(i->contextId);
- ctx->getCpuPtr()->wakeup(ctx->threadId());
+ ContextID owner_cid = i->contextId;
+ ContextID requester_cid = pkt->req->contextId();
+ if (owner_cid != requester_cid) {
+ ThreadContext* ctx = system()->getThreadContext(owner_cid);
+ TheISA::globalClearExclusive(ctx);
+ }
i = lockedAddrList.erase(i);
} else {
i++;
} else if (pkt->isRead()) {
assert(!pkt->isWrite());
if (pkt->isLLSC()) {
+ assert(!pkt->fromCache());
+ // if the packet is not coming from a cache then we have
+ // to do the LL/SC tracking here
trackLoadLocked(pkt);
}
if (pmemAddr)
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