(no commit message)

diff --git a/3d_gpu/architecture/dynamic_simd.mdwn b/3d_gpu/architecture/dynamic_simd.mdwn
index fa0ba58ddee8a69befd42cf7c3467559d10ef65c..3efdba7ca172738262b1f7c0b03055d8e69c5813 100644 (file)
--- a/3d_gpu/architecture/dynamic_simd.mdwn
+++ b/3d_gpu/architecture/dynamic_simd.mdwn
@@ -325,7 +325,7 @@ has two different inter-related abstraction levels.
   to use macro substitution or crude compilers to autogenerate the dynamic
   SIMD from VHDL / Verilog templates, why not do exactly the same thing.
   Design a SIMD HDL language, write python in that, and have it output
-  nmigen HDL.
+  python source code with nmigen HDL.
 
 All of these ideas, unfortunately, are extremely costly in many different ways: