xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.

Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 590fe61d2a5a77a8645519c44ca2ab4f22a98d3a..b27c085291fd679af6479885fb7f0696320f0f2b 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -235,10 +235,9 @@ struct SynthXilinxPass : public Pass
 
                if (check_label(active, run_from, run_to, "map_cells"))
                {
+                       Pass::call(design, "techmap -map +/xilinx/cells_map.v");
                        if (vpr)
-                           Pass::call(design, "techmap -D NO_LUT -map +/xilinx/cells_map.v");
-                       else
-                           Pass::call(design, "techmap -map +/xilinx/cells_map.v");
+                           Pass::call(design, "techmap -map +/xilinx/lut2lut.v");
                        Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT");
                        Pass::call(design, "clean");
                }