ARM: Add a register, immediate, immediate to register base for [su]bfx.

diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 3ad49bb9d7b9e7cbbb9f4bbf742a7ab1cff0e07c..20f102e729ba268849459d475e6a4ce392fefa80 100644 (file)
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -196,6 +196,18 @@ RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     return ss.str();
 }
 
+std::string
+RegRegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    printMnemonic(ss);
+    printReg(ss, dest);
+    ss << ", ";
+    printReg(ss, op1);
+    ccprintf(ss, ", #%d, #%d", imm1, imm2);
+    return ss.str();
+}
+
 std::string
 RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {

diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index 7ee2d95f97c47c0570e5d6faca5625f86840ada0..b5a75d20db99f43241f0f5ce462f0620e8bbc1f0 100644 (file)
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -176,6 +176,24 @@ class RegRegRegOp : public PredOp
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
+class RegRegImmImmOp : public PredOp
+{
+  protected:
+    IntRegIndex dest;
+    IntRegIndex op1;
+    uint32_t imm1;
+    uint32_t imm2;
+
+    RegRegImmImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+                   IntRegIndex _dest, IntRegIndex _op1,
+                   uint32_t _imm1, uint32_t _imm2) :
+        PredOp(mnem, _machInst, __opClass),
+        dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
+    {}
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
 class RegImmRegShiftOp : public PredOp
 {
   protected:

diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index 7a9a35ec9c60c25a0c478948d7f7b7f6a24982bd..83d165365fea1a001d47329b299f21e496f54221 100644 (file)
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -196,6 +196,32 @@ def template RegRegRegOpConstructor {{
     }
 }};
 
+def template RegRegImmImmOpDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+  protected:
+    public:
+        // Constructor
+        %(class_name)s(ExtMachInst machInst,
+                       IntRegIndex _dest, IntRegIndex _op1,
+                       uint32_t _imm1, uint32_t _imm2);
+        %(BasicExecDeclare)s
+};
+}};
+
+def template RegRegImmImmOpConstructor {{
+    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+                                          IntRegIndex _dest,
+                                          IntRegIndex _op1,
+                                          uint32_t _imm1,
+                                          uint32_t _imm2)
+        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+                         _dest, _op1, _imm1, _imm2)
+    {
+        %(constructor)s;
+    }
+}};
+
 def template RegImmRegOpDeclare {{
 class %(class_name)s : public %(base_class)s
 {