radv/gfx10: implement radv_pipeline_generate_geometry_shader()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 79d71d2259e6cd31241d3f502ef4f98a5c2ebcce..44de1aad6742d9a892e29fe5bd091ad0de181f1f 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3210,9 +3210,15 @@ radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
        va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
 
        if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
-               radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
-               radeon_emit(cs, va >> 8);
-               radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
+               if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
+                       radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
+                       radeon_emit(cs, va >> 8);
+                       radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
+               } else {
+                       radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
+                       radeon_emit(cs, va >> 8);
+                       radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
+               }
 
                radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
                radeon_emit(cs, gs->config.rsrc1);