Fixes for ll/sc for the O3 model.

cpu/o3/alpha_cpu.hh:
    Store conditionals should not write their data to memory if they failed.
cpu/o3/lsq_unit.hh:
    Setup request parameters when they're needed.

--HG--
extra : convert_revision : d75cd7deda03584b7e25cb567e4d79032cac7118

diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index 68e149e77ce7b64570fe9b887362307b682eabe4..dfdf092ed4485d852059572bb7f6005ddee96fbc 100644 (file)
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -425,9 +425,10 @@ class AlphaFullCPU : public FullO3CPU<Impl>
                 req->result = 2;
             } else {
                 if (this->lockFlag/* && this->lockAddr == req->paddr*/) {
-                    req->result=1;
+                    req->result = 1;
                 } else {
                     req->result = 0;
+                    return NoFault;
                 }
             }
         }

diff --git a/cpu/o3/lsq_unit.hh b/cpu/o3/lsq_unit.hh
index 73c485ce97c1bcb9d809db500386ce47c4785853..ba8b1d2e2d87d6de6b77028f42efc6de0160c14c 100644 (file)
--- a/cpu/o3/lsq_unit.hh
+++ b/cpu/o3/lsq_unit.hh
@@ -566,6 +566,9 @@ LSQUnit<Impl>::read(MemReqPtr &req, T &data, int load_idx)
     DPRINTF(LSQUnit, "Doing functional access for inst PC %#x\n",
             loadQueue[load_idx]->readPC());
     assert(!req->data);
+    req->cmd = Read;
+    req->completionEvent = NULL;
+    req->time = curTick;
     req->data = new uint8_t[64];
     Fault fault = cpu->read(req, data);
     memcpy(req->data, &data, sizeof(T));
@@ -587,9 +590,6 @@ LSQUnit<Impl>::read(MemReqPtr &req, T &data, int load_idx)
         }
         DPRINTF(LSQUnit, "Doing timing access for inst PC %#x\n",
                 loadQueue[load_idx]->readPC());
-        req->cmd = Read;
-        req->completionEvent = NULL;
-        req->time = curTick;
 
         assert(!req->completionEvent);
         req->completionEvent =