uart/sim: add pty (optional, to use flterm)

diff --git a/misoclib/com/uart/phy/sim.py b/misoclib/com/uart/phy/sim.py
index c628ea92e00d8668c3b6128a3ed31161cbf2e984..faae3d6ed6bec34ff78fd367e433952451da73c3 100644 (file)
--- a/misoclib/com/uart/phy/sim.py
+++ b/misoclib/com/uart/phy/sim.py
@@ -1,3 +1,5 @@
+import os, pty, time
+
 from migen.fhdl.std import *
 from migen.flow.actor import Sink, Source
 
@@ -15,3 +17,14 @@ class UARTPHYSim(Module):
                        self.source.data.eq(pads.sink_data),
                        pads.sink_ack.eq(self.source.ack)
                ]
+
+               m, s = pty.openpty()
+               name = os.ttyname(s)
+               print("UART tty: "+name)
+               time.sleep(0.5) # pause for user
+               f = open("/tmp/simserial", "w")
+               f.write(os.ttyname(s))
+               f.close()
+
+       def do_exit(self, *args, **kwargs):
+               os.remove("/tmp/simserial")