Merge gblack@m5.eecs.umich.edu:/bk/multiarch

into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : d8626acb2686e123ad0bb6cf94e85c992657470d

diff --cc arch/alpha/isa/main.isa
Simple merge

diff --cc arch/alpha/isa/mem.isa
index 1889daefcd4ecd934095eb62090886103f305212,1f6907181794c4a99732cd10edb54400b0a34ec2..19785e3a85ef5be5f4435afbea23dfd64a5a76b5
--- 1/arch/alpha/isa/mem.isa
--- 2/arch/alpha/isa/mem.isa
+++ b/arch/alpha/isa/mem.isa
@@@ -282,56 -267,8 +282,56 @@@ def template LoadExecute {
  }};
  
  
 +def template LoadInitiateAcc {{
 +    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
 +                                      Trace::InstRecord *traceData) const
 +    {
 +        Addr EA;
 +        Fault fault = No_Fault;
 +        %(mem_acc_type)s Mem = 0;
 +
 +        %(fp_enable_check)s;
 +        %(op_src_decl)s;
 +        %(op_rd)s;
 +        %(ea_code)s;
 +
 +        if (fault == No_Fault) {
 +            fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
 +        }
 +
 +        return fault;
 +    }
 +}};
 +
 +
 +def template LoadCompleteAcc {{
 +    Fault %(class_name)s::completeAcc(uint8_t *data,
 +                                      %(CPU_exec_context)s *xc,
 +                                      Trace::InstRecord *traceData) const
 +    {
 +        Fault fault = No_Fault;
 +        %(mem_acc_type)s Mem = 0;
 +
 +        %(fp_enable_check)s;
 +        %(op_dest_decl)s;
 +
 +        memcpy(&Mem, data, sizeof(Mem));
 +
 +        if (fault == No_Fault) {
 +            %(memacc_code)s;
 +        }
 +
 +        if (fault == No_Fault) {
 +            %(op_wb)s;
 +        }
 +
 +        return fault;
 +    }
 +}};
 +
 +
  def template StoreMemAccExecute {{
-     Fault
+     Fault *
      %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
                                     Trace::InstRecord *traceData) const
      {
@@@ -402,63 -339,9 +402,63 @@@ def template StoreExecute {
      }
  }};
  
 +def template StoreInitiateAcc {{
 +    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
 +                                      Trace::InstRecord *traceData) const
 +    {
 +        Addr EA;
 +        Fault fault = No_Fault;
 +        uint64_t write_result = 0;
 +        %(mem_acc_type)s Mem = 0;
 +
 +        %(fp_enable_check)s;
 +        %(op_src_decl)s;
 +        %(op_rd)s;
 +        %(ea_code)s;
 +
 +        if (fault == No_Fault) {
 +            %(memacc_code)s;
 +        }
 +
 +        if (fault == No_Fault) {
 +            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
 +                              memAccessFlags, &write_result);
 +            if (traceData) { traceData->setData(Mem); }
 +        }
 +
 +        return fault;
 +    }
 +}};
 +
 +
 +def template StoreCompleteAcc {{
 +    Fault %(class_name)s::completeAcc(uint8_t *data,
 +                                      %(CPU_exec_context)s *xc,
 +                                      Trace::InstRecord *traceData) const
 +    {
 +        Fault fault = No_Fault;
 +        uint64_t write_result = 0;
 +
 +        %(fp_enable_check)s;
 +        %(op_dest_decl)s;
 +
 +        memcpy(&write_result, data, sizeof(write_result));
 +
 +        if (fault == No_Fault) {
 +            %(postacc_code)s;
 +        }
 +
 +        if (fault == No_Fault) {
 +            %(op_wb)s;
 +        }
 +
 +        return fault;
 +    }
 +}};
 +
  
  def template MiscMemAccExecute {{
-     Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
+     Fault * %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
                                            Trace::InstRecord *traceData) const
      {
          Addr EA;

diff --cc sim/syscall_emul.hh
Simple merge