cpu: Remove ExtMachInst typedefs from the O3 CPU model.

These typedefs aren't used, and they expose ISA specific types outside
the ISA implementations.

Change-Id: I64b9cec18d6f92765eebbdf8c8f1de15c0deba34
Reviewed-on: https://gem5-review.googlesource.com/9404
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 8a0ae1d56d628c5818c9c2144f303ba8a4cc7174..47dc830e0b83dbee884153b0fec7c805e8b94ac6 100644 (file)
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -65,8 +65,6 @@ class BaseO3DynInst : public BaseDynInst<Impl>
 
     /** Binary machine instruction type. */
     typedef TheISA::MachInst MachInst;
-    /** Extended machine instruction type. */
-    typedef TheISA::ExtMachInst ExtMachInst;
     /** Register types. */
     typedef TheISA::IntReg   IntReg;
     typedef TheISA::FloatReg FloatReg;

diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 672fb499be63a7861449c5f1252409ed3a158641..4382197f499d7013814f8a4c64895dbdac52227c 100644 (file)
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -83,7 +83,6 @@ class DefaultFetch
 
     /** Typedefs from ISA. */
     typedef TheISA::MachInst MachInst;
-    typedef TheISA::ExtMachInst ExtMachInst;
 
     class FetchTranslation : public BaseTLB::Translation
     {