+2015-03-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR ld/18160
+ * elflink.c (elf_gc_sweep): Skip if relocation is incompatible.
+ (bfd_elf_gc_sections): Likewise.
+
2015-03-25 Marcus Shawcroft <marcus.shawcroft@arm.com>
* elfnn-aarch64.c (_bfd_aarch64_resize_stubs): Adjust stub section
{
asection *o;
- if (bfd_get_flavour (sub) != bfd_target_elf_flavour)
+ if (bfd_get_flavour (sub) != bfd_target_elf_flavour
+ || !(*bed->relocs_compatible) (sub->xvec, abfd->xvec))
continue;
for (o = sub->sections; o != NULL; o = o->next)
{
asection *o;
- if (bfd_get_flavour (sub) != bfd_target_elf_flavour)
+ if (bfd_get_flavour (sub) != bfd_target_elf_flavour
+ || !(*bed->relocs_compatible) (sub->xvec, abfd->xvec))
continue;
/* Start at sections marked with SEC_KEEP (ref _bfd_elf_gc_keep).
+2015-03-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR ld/18160
+ * ld-x86-64/pr18160.d: New file.
+ * ld-x86-64/pr18160.s: Likewise.
+ * ld-x86-64/pr18160.t: Likewise.
+ * ld-x86-64/x86-64.exp: Run pr18160.
+---
2015-03-25 Marcus Shawcroft <marcus.shawcroft@arm.com>
* ld-aarch64/erratum835769.d: Adjust for initial branch over stub
--- /dev/null
+#as: --64
+#ld: --gc-sections -melf_x86_64 -T pr18160.t
+#objdump: -dw
+
+.*: +file format elf32-i386
+
+
+Disassembly of section .text:
+
+0+ <start>:
+[ ]*[a-f0-9]+: e9 00 00 00 00 jmp 5 <foo>
+
+0+5 <foo>:
+[ ]*[a-f0-9]+: c3 ret
--- /dev/null
+ .section .text.start,"ax",@progbits
+ .globl start
+ .type start, @function
+start:
+ .cfi_startproc
+ jmp foo
+ .cfi_endproc
+ .size start, .-start
+ .section .text.foo,"ax",@progbits
+ .globl foo
+ .type foo, @function
+foo:
+ .cfi_startproc
+ ret
+ .cfi_endproc
+ .size foo, .-foo
--- /dev/null
+OUTPUT_FORMAT(elf32-i386)
+ENTRY(start)
+SECTIONS
+{
+ .text : { *(.text*) }
+ .data : { *(.data.*) }
+ .bss : { *(.bss.*) }
+}
run_dump_test "mov1d"
run_dump_test "pr17935-1"
run_dump_test "pr17935-2"
+run_dump_test "pr18160"
# Must be native with the C compiler
if { [isnative] && [which $CC] != 0 } {