Skip $inout transformation if not a PI

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index c080cca4dd17d6d41ec2da1b569e6b5144641e6d..6ca24bd7e6cf8b8111d55a599fda5fd3c0466e87 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -542,10 +542,12 @@ struct XAigerWriter
                                undriven_bits.erase(bit);
                        }
 
-               // For inout ports, or keep-ed wires, then create a new wire with an
-               // $inout.out suffix, make it a PO driven by the existing inout, and
-               // inherit existing inout's drivers
+               // For inout ports, or keep-ed wires, that end up as both a PI and a
+               // PO, then create a new PO with an $inout.out suffix that is driven
+               // by the existing inout, and inherit its drivers
                for (auto bit : inout_bits) {
+                       if (!input_bits.count(bit))
+                               continue;
                        RTLIL::Wire *wire = bit.wire;
                        RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str());
                        RTLIL::Wire *new_wire = module->wire(wire_name);