minor fixes

diff --git a/misoc/integration/builder.py b/misoc/integration/builder.py
index 0e1ed054f9cb04b8e389d951413b46285d3644d6..e0ecce6e727e988c9c532de67a222b630a19c776 100644 (file)
--- a/misoc/integration/builder.py
+++ b/misoc/integration/builder.py
@@ -88,7 +88,7 @@ class Builder:
                 subprocess.check_call(["make", "-C", dst_dir])
 
     def _initialize_rom(self):
-        bios_file = os.path.join(self.output_dir, "software" "bios",
+        bios_file = os.path.join(self.output_dir, "software", "bios",
                                  "bios.bin")
         if self.soc.integrated_rom_size:
             with open(bios_file, "rb") as boot_file:

diff --git a/misoc/interconnect/wishbone2csr.py b/misoc/interconnect/wishbone2csr.py
index 17911abd2fc32d8100722d7205a168e7482eb920..b065724a154e0cd214cd213dcaa5a33c57708284 100644 (file)
--- a/misoc/interconnect/wishbone2csr.py
+++ b/misoc/interconnect/wishbone2csr.py
@@ -1,7 +1,7 @@
 from migen import *
 from migen.genlib.misc import timeline
 
-from misoc.interconnect import csr, wishbone
+from misoc.interconnect import csr_bus, wishbone
 
 
 class WB2CSR(Module):
@@ -10,7 +10,7 @@ class WB2CSR(Module):
             bus_wishbone = wishbone.Interface()
         self.wishbone = bus_wishbone
         if bus_csr is None:
-            bus_csr = csr.Interface()
+            bus_csr = csr_bus.Interface()
         self.csr = bus_csr
 
         ###