(no commit message)

diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn
index ab0f2201a56e95abca2b2ddec9f6550a5c061130..8d94d2ecdc083fee4a4b19c742ad4c02e7702bc0 100644 (file)
--- a/openpower/sv/biginteger/analysis.mdwn
+++ b/openpower/sv/biginteger/analysis.mdwn
@@ -227,8 +227,8 @@ which are scalar initialisation:
 
     li r16, 0                     # zero accumulator
     addic r16, r16, 0             # CA to zero as well
-    sv.madde r0.v, r8.v, r17, r16 # mul vector
-    sv.adde r24.v, r24.v, r0.v   # big-add row to result
+    sv.maddedu *r0, *r8, r17, r16 # mul vector
+    sv.adde *r24, *r24, *r0   # big-add row to result
 
 Normally, in a Scalar ISA, the use of a register as both a source
 and destination like this would create costly Dependency Hazards, so